TB2118F Просмотр технического описания (PDF) - Toshiba

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производитель

TB2118F

High Speed PLL For DTS (Bi−CMOS Integrated Circuit Silicon Monolithic)

Toshiba 

3) Serial data transfer formats

· Data input mode (at input, DOUT becomes high impedance.)

CE

CK

DIN

Internal

data

0.5 µs min. 1 µs min.

0.5 µs min.

0.5 µs min.

Can be omitted

0.5 µs min.

〃 〃 〃 〃 A0 A1 A2 A3 D0 D1 D2 D3 D4 D5

Can be omitted

Input address

(Note) ● When power for TB2118F is fully on, input data after 100ms or more.

● Until data input starts, set the CE pin to GND to avoid any noise input.

● Data output mode

CE

CK

Can be omitted

TB2118F

End

0.5 µs min.

D36 D37 D38 D39 D40 〃

0.1 µs max.

End

DIN

DOUT

〃 〃 〃 〃 A0 A1 A2 A3

Can be omitted

Output address

(high impedance)

0.1 µs max. (low level)

D0 D1 D2 D3 D4 D5

Internal registers preset

By pull−up resistor value

(high level)

D20 D21 D22 D23 D24

(high impedance)

(Note) ● Normally, DOUT is high impedance.

● During data output, data output mode is terminated by changing CE = H to L.

8

2002-10-30

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