CXD1807Q Просмотр технического описания (PDF) - Sony Semiconductor

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Компоненты Описание

производитель

CXD1807Q

CD-G Decoder

Sony Semiconductor 

CXD1807Q

Description of Functions

1. Pin Description

1-1. Subcode data interface

Inputs subcode data and subcode sync detection signals using the following pins. These pins can be directly

connected to Sony signal processing LSI for CD.

1) SCOR

Inputs the signal that indicates detection of either subcode sync S0 or S1. Connect this pin to the SCOR

pin of CD DSP.

2) WFCK

Inputs WFCK (Write Frame Clock). Connect this pin to the WFCK pin of CD DSP.

3) EXCK

Outputs the clock to read data from the SBSO pin. Connect this pin to the EXCK pin of CD DSP.

4) SBSO

Serially inputs the subcode data P to W. Connect this pin to the SBSO pin of CD DSP.

5) MUTE

Inputs the signal to mute subcode data inputs. This pin is in the mute state when High signal is input.

1-2. CPU interface

Inputs data and sends commands to the CXD1807Q using the following pins.

1) CLK

Inputs the clock to input serial data from the external CPU.

2) DIN

Inputs serial data from the external CPU.

3) XLT

Inputs the signal to latch serial data from the external CPU. The pin latches serial data at the falling edge

of this signal.

1-3. DRAM interface

The screen data are stored in the external DRAM. The DRAM read/write function is controlled using the

following pins. Use a 64K × 4-bit DRAM with an access time of 100ns or less.

1) RAS1

Indicates the row address is effective. Connect this pin to the RAS pin of the external DRAM.

2) CAS1

Indicates the column address is effective. Connect this pin to the CAS pin of the external DRAM.

3) A10 to A17 (8 pins)

Outputs DRAM addresses. Connect these pins to the A0 to A7 pins of the external DRAM, respectively.

4) D10 to D13 (4 pins)

Inputs and outputs DRAM data. Connect these pins to the D0 to D3 pins of the external DRAM,

respectively.

5) WE1

Outputs the write enable signal of DRAM. Connect this pin to the WE pin of the external DRAM.

6) OE1

Outputs the output enable signal of DRAM. Connect this pin to the OE pin of the external DRAM.

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