SY87701ALHG Просмотр технического описания (PDF) - Micrel

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производитель

SY87701ALHG

3.3V 28Mbps to 1.3Gbps AnyRate® Clock and Data Recovery

Micrel 

Micrel, Inc.

SY87701AL

PIN DESCRIPTIONS

Pin Number

SOIC

4

5

Pin Number

TQFP

2

3

Pin Name

RDINP

RDINN

7

5

REFCLK

27

26

CD

6

4

FREQSEL1

8

6

FREQSEL2

9

7

FREQSEL3

3

32

DIVSEL1

26

25

DIVSEL2

17

16

CLKSEL

2

31

LFIN

25

24

RDOUTP

24

23

RDOUTN

22

21

RCLKP

21

20

RCLKN

19

18

TCLKP

18

17

TCLKN

11

12

16

15

28

1

20, 23

13, 14

10

13

9

10

15

14

27, 28,

29, 30

19, 22

12, 13

1, 8

11

PLLSP

PLLSN

PLLRP

PLLRN

VCC

VCCA

VCCO

GND

NC

GNDA

Note:

1. VCC, VCCA, VCCO must be the same value.

M9999-082107

hbwhelp@micrel.com or (408) 955-1690

Pin Function

Serial Data Input (Differential PECL): These built-in line receiver inputs are

connected to the differential receive serial data stream. An internal receive PLL

recovers the embedded clock (RCLK) and data (RDOUT) information. The

incoming data rate can be within one of eight frequency ranges depending on the

state of the FREQSEL pins. See “Frequency Selection” table.

Reference Clock (TTL Inputs): This input is used as the reference for the internal

frequency synthesizer and the “training” frequency for the receiver PLL to keep it

centered in the absence of data coming in on the RDIN inputs.

Carrier Detect (PECL Input): This input controls the recovery function of the

Receive PLL and can be driven by the carrier detect output of optical modules or

from external transition detection circuitry. When this input is HIGH the input data

stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW

the data on the inputs RDIN will be internally forced to a constant LOW, the data

outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW

and the clock recovery PLL forced to look onto the clock frequency generated from

REFCLK.

Frequency Select (TTL Inputs): These inputs select the output clock frequency

range as shown in the “Frequency Selection” table.

Divider Select (TTL Inputs): These inputs select the ratio between the output clock

frequency (RCLK/TCLK) and the REFCLK input frequency as shown in the

“Reference Frequency Selection” table.

Clock Select (TTL Inputs): This input is used to select either the recovered clock

of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer

(CLKSEL = LOW) to the TCLK outputs.

Link Fault Indicator (TTL Output): This output indicates the status of the input data

stream RDIN. Active HIGH signal is indicating when the internal clock recovery

PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH

and RDIN is within the frequency range of the Receive PLL (1000ppm).

Receive Data Output (Differential PECL): These ECL 100k outputs represent the

recovered data from the input data stream (RDIN). This recovered data is specified

against the rising edge of RCLK. These outputs must be terminated with 50Ω to

VCC–2 or equivalent. Thhis applies even if these outputs are not used.

Clock Output (Differential PECL): These ECL 100k outputs represent the

recovered clock used to sample the recovered data (RDOUT).

Clock Output (Differential PECL): These ECL 100k outputs represent either the

recovered clock (CLKSEL = HIGH) used to sample the recovered data (RDOUT) or

the transmit clock of the frequency synthesizer (CLKSEL = LOW). These outputs

must be terminated with 50Ω to VCC–2 or equivalent. This applies even if these

outputs are not used.

Clock Synthesis PLL Loop Filter. External loop filter pins for the clock synthesis

PLL.

Clock Recovery PLL Loop Filter. External loop filter pins for the receiver PLL.

Supply Voltage(1)

Analog Supply Voltage(1)

Output Supply Voltage(1)

Ground

No Connect

Analog Ground

3

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