SX1233 Просмотр технического описания (PDF) - Semtech Corporation

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производитель

SX1233

High Bit Rate Transceiver Low Power Integrated UHF Transceiver

Semtech Corporation 

SX1233

ADVANCED COMMUNICATIONS & SENSING

Table of contents

Section

DATASHEET

Page

Figure 39. +13dBm Schematic .....................................................................................................................................76

Figure 40. +17dBm Schematic .....................................................................................................................................77

Figure 41. Package Outline Drawing ............................................................................................................................78

Figure 42. Recommended Land Pattern ......................................................................................................................78

Figure 43. Tape & Reel Specification ...........................................................................................................................79

Index of Tables

Table 1. SX1233 Pinouts ...............................................................................................................................................10

Table 2. Absolute Maximum Ratings .............................................................................................................................11

Table 3. Operating Range .............................................................................................................................................11

Table 4. Power Consumption Specification ...................................................................................................................12

Table 5. Frequency Synthesizer Specification ..............................................................................................................12

Table 6. Receiver Specification .....................................................................................................................................13

Table 7. Transmitter Specification .................................................................................................................................14

Table 8. Digital Specification .........................................................................................................................................15

Table 9. Bit Rate Examples ...........................................................................................................................................20

Table 10. Power Amplifier Mode Selection Truth Table ................................................................................................21

Table 11. LNA Gain Settings .........................................................................................................................................23

Table 12. Receiver Performance Summary ..................................................................................................................25

Table 13. Available RxBw Settings ................................................................................................................................26

Table 14. Basic Transceiver Modes ..............................................................................................................................35

Table 15. Range of Durations in Listen Mode ...............................................................................................................39

Table 16. Signal Acceptance Criteria in Listen Mode ....................................................................................................40

Table 17. End of Listen Cycle Actions ...........................................................................................................................40

Table 18. Status of FIFO when Switching Between Different Modes of the Chip .........................................................46

Table 19. DIO Mapping, Continuous Mode ...................................................................................................................48

Table 20. DIO Mapping, Packet Mode ..........................................................................................................................48

Table 21. Registers Summary .......................................................................................................................................60

Table 22. Common Configuration Registers .................................................................................................................63

Table 23. Transmitter Registers ....................................................................................................................................66

Table 24. Receiver Registers ........................................................................................................................................67

Table 25. IRQ and Pin Mapping Registers ....................................................................................................................69

Table 26. Packet Engine Registers ...............................................................................................................................71

Table 27. Temperature Sensor Registers .....................................................................................................................74

Table 28. Test Registers ...............................................................................................................................................74

Table 29. Crystal Specification ......................................................................................................................................75

Table 30. Revision History .............................................................................................................................................80

Rev 3.April 2010

Page 6

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