SX1211I084TRT(2007) Просмотр технического описания (PDF) - Semtech Corporation

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SX1211I084TRT
(Rev.:2007)

Lowest Power Integrated UHF Transceiver Short Range Devices

Semtech Corporation 

ADVANCED COMMUNICATIONS & SENSING

SX1211

Table of Contents

1. Block Diagram and General Description ........................ 5

1.1. Simplified Block Diagram ............................................ 5

1.2. Pin Diagram ................................................................ 6

1.3. Pin Description............................................................ 7

2. Electrical Characteristics................................................ 8

2.1. ESD Notice ................................................................. 8

2.2. Absolute Maximum Ratings ........................................ 8

2.3. Operating Range......................................................... 8

2.4. Chip Specification ....................................................... 8

2.4.1. Power Consumption................................................. 8

2.4.2. Frequency Synthesis................................................ 9

2.4.3. Transmitter............................................................... 9

2.4.4. Receiver................................................................. 10

2.4.5. Digital Specification................................................ 11

3. Architecture Description............................................... 12

3.1. Power Supply Strategy.............................................. 12

3.2. Frequency Synthesis Description.............................. 12

3.2.1. Crystal Resonator Specification ............................. 12

3.2.2. CLKOUT Output..................................................... 13

3.2.3. PLL Architecture .................................................... 13

3.2.4. PLL Tradeoffs ........................................................ 14

3.2.5. Voltage Controlled Oscillator.................................. 14

3.2.6. PLL Loop Filter....................................................... 15

3.2.7. PLL Lock Detection Indicator ................................. 16

3.2.8. Frequency Calculation ........................................... 16

3.2.9. Software for Frequency Calculation ....................... 16

3.3. Transmitter Description ............................................. 18

3.3.1. Architecture Description ......................................... 18

3.3.2. Bit Rate Setting ...................................................... 19

3.3.3. Fdev Setting in FSK Mode ..................................... 19

3.3.4. Fdev Setting in OOK Mode .................................... 19

3.3.5. Suggested Interpolation Filter Setting .................... 19

3.3.6. Power Amplifier...................................................... 20

3.3.7. Transmitter Spectral Purity..................................... 22

3.3.8. Common Input and Output Front-End.................... 22

3.4. Receiver Description................................................. 24

3.4.1. Architecture............................................................ 24

3.4.2. LNA and First Mixer ............................................... 25

3.4.3. IF Gain and Second I/Q Mixer................................ 25

3.4.4. Channel Filters....................................................... 25

3.4.5. Channel Filters Setting in FSK Mode ..................... 27

3.4.6. Channel Filters Setting in OOK Mode .................... 27

3.4.7. RSSI....................................................................... 27

3.4.8. Fdev Setting in Receive Mode ............................... 28

3.4.9. FSK Demodulator .................................................. 29

3.4.10. OOK Demodulator................................................ 29

3.4.11. Bit Synchronizer................................................... 31

3.4.12. Data Output.......................................................... 32

4. Data Processing........................................................... 33

4.1. Overview ................................................................... 33

4.1.1. Block Diagram........................................................ 33

4.1.2. Data Operation Modes ........................................... 33

4.2. Building Blocks Description....................................... 34

4.2.1. SPI Interface .......................................................... 34

4.2.2. FIFO....................................................................... 37

4.2.3. Sync Word Recognition ..........................................39

4.2.4. Packet Handler .......................................................39

4.2.5. Control ....................................................................39

4.3. Continuous Mode ......................................................40

4.3.1. General Description ................................................40

4.3.2. Tx Processing.........................................................40

4.3.3. Rx Processing ........................................................40

4.3.4. Interrupt Signals Mapping.......................................41

4.3.5. uC Connections ......................................................41

4.3.6. Example of Usage ..................................................42

4.4. Buffered Mode ...........................................................42

4.4.1. General Description ................................................42

4.4.2. Tx Processing.........................................................43

4.4.3. Rx Processing ........................................................44

4.4.4. Interrupt Signals Mapping.......................................45

4.4.5. uC Connections ......................................................46

4.4.6. Example of Usage ..................................................46

4.5. Packet Mode..............................................................47

4.5.1. General Description ................................................47

4.5.2. Packet Format ........................................................48

4.5.3. Tx Processing.........................................................49

4.5.4. Rx Processing ........................................................49

4.5.5. Packet Filtering.......................................................50

4.5.6. DC-Free Data Mechanisms ....................................51

4.5.7. Interrupt Signal Mapping.........................................52

4.5.8. uC Connections ......................................................53

4.5.9. Example of Usage ..................................................53

4.5.10. Additional Information ...........................................54

5. Operating Modes ..........................................................55

5.1. Modes of Operation ...................................................55

5.2. Digital Pin Configuration vs. Chip Mode ....................55

5.3. Switching Times and Procedures ..............................55

5.3.1. Optimized Receive Cycle........................................56

5.3.2. Optimized Transmit Cycle.......................................57

5.3.3. Transmitter Frequency Hop Optimized Cycle .........58

5.3.4. Receiver Frequency Hop Optimized Cycle .............59

5.3.5. Rx Tx and Tx Rx Jump Cycles ..........................60

5.4. Power-On Reset ........................................................60

6. Configuration and Status Registers ..............................61

6.1. General Description...................................................61

6.2. Main Configuration Register - MCParam ...................61

6.3. Interrupt Configuration Parameters - IRQParam .......63

6.4. Receiver Configuration parameters - RXParam ........65

6.5. Sync Word Parameters - SYNCParam ......................66

6.6. Transmitter Parameters - TXParam...........................67

6.7. Oscillator Parameters - OSCParam...........................67

6.8. Packet Handling Parameters – PKTParam................68

7. Reference Design.........................................................69

7.1. Schematics ................................................................69

7.2. PCB Layout ...............................................................69

7.3. Bill Of Material ...........................................................70

7.4. SAW Filter Plot ..........................................................71

8. Packaging Information..................................................72

9. Contact Information ......................................................73

V3.0 – august 15th, 2007

Page 2 of 73

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