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ML53612 Просмотр технического описания (PDF) - Oki Electric Industry

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ML53612 Datasheet PDF : 68 Pages
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1.0 FEATURES
• High functionality, low cost implementation of
the ECTF H.100/H.110 interoperability
specifications.
• Simple to connect PCI and cPCI™ board-level
circuitry to the universally accepted CT Bus™.
• Ultra slim profiling (176-pin LQFP package).
• Up to 128 programmable connections (64
transmit and 64 receive) to any of the 4096 time-
slots on the H.100/H.110 CT Bus.
• 8-channel stream-to-stream switching for data
stream connections at variable rates.
• Implementation of all compatibility signals for
complete interoperability with existing 4 MHz
SCbus™, 8 MHz SCbus, 2 MHz MVIP-90™
devices, and H-MVIP™.
• Master PLL meets AT&T 62411 MTIE and jitter
attenuation requirements to provides reliable
clock synchronization for network-grade
connection to digital network interfaces.
• Supports all H.100/H.110 CT Bus clock fallback
features.
• Choice of constant or minimum switching
delay on a per time-slot basis.
• 3.3 V I/O with 5 V tolerant input.
• Supports multiplexed and nonmultiplexed
address/data bus modes for both Intel and
Motorola microprocessors.
• Supports CT Bus optional message channel
interface, for both H.100 (PCI) and H.110 (cPCI)
applications.
• Supports a variety of framing formats via a
configurable local bus.
• Efficient microprocessor interface access to
Local and CT Bus data streams through direct
parallel access to/from transmit and receive
switch.
• Direct Parallel Access to/from Transmit and
Receive switch allows efficient microprocessor
interface access to local and CT Bus data
streams.
1.1 Applications
• Low- to medium-density computer telephony hardware (PCI and cPCI platforms)
• Enhanced service platforms
• Private branch exchanges (PBXs)
• Wireless base stations
• Internet telephony systems
• Digital trunking equipment
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