STW8009 Просмотр технического описания (PDF) - STMicroelectronics
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STW8009 Datasheet PDF : 55 Pages
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Ball/pin information
3
Ball/pin information
STw8009/STw8019
Table 1.
Ball
E1
D2
C1
D1
G4
E4
A3
A5
A7
B7
B3
B5
C5
B4
B6
A4
G2
G7, G6,
F7, F6,
E7, E6,
D7, D6
Product name ball functions
Name
Type
Vdd
Power
Gndd
GND
Vdd_IO1
Power
Vss_IO1
GND
Vdd_IO2
Vss_IO2
Power
GND
VccA1
Power
VccA2
Power
VccA3
VccA4
Power
Power
GNDA1
GND
GNDA2
GND
GNDA3
GND
GNDA4
GNDA5
GND
GND
Rext
Analog
CLK
Digital Input
YCbCr[0:7]
Digital Input
G5
Hsync
Digital I/O
Vsync
F5
Digital I/O
Odd/Even
F3
SDA
Digital I/O
G3
SCL
Digital Input
E3
Add
Digital input
C7
PORn
Digital input
F2
Suspend
Digital input
Voltage
1.2 V
0V
1.8 V
0V
1.8 V
0V
2.8 /3.3V
2.8 /3.3 V
2.8 /3.3 V
2.8 /3.3 V
0V
0V
0V
0V
0V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
Description
Digital core chip supply
Digital core chip ground
Digital I/O supply
Digital I/O ground
Digital I/O supply
Digital I/O ground
DAC1 matrix analog power supply
DAC2 matrix analog power supply
2.8/3.3 V digital feature supply
2.8 /3.3 V digital feature supply
DAC1 ground
DAC2 ground
2.8 /3.3 V digital feature ground
Rext ground connection
Analog ground
DAC current reference setting
27 MHz master pixel clock (pixclk)
Time multiplexed 4:2:2 luminance and
chrominance data as defined in CCIR 601
and CCIR 656 (excepted for TTL input
signals)
Horizontal Synchronization signal:
- Input in slave mode, except when sync is
extracted from YcbCr data
- Output in master mode and when sync is
extracted from YcbCr signal.
Vertical Synchronization – Odd/Even signal:
- Input in slave mode, except when sync is
extracted from YcbCr data
- Output in master mode and when sync is
extracted from YcbCr signal.
2 wire serial MPU data line
2 wire serial MPU clock
Device address selection
Power On Reset (Active low)
Suspend input
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