STK672-740B-E Просмотр технического описания (PDF) - SANYO -> Panasonic

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Компоненты Описание

производитель

STK672-740B-E

2-phase Stepping Motor Driver

SANYO -> Panasonic 

Sample Application Circuit

STK672-740B-E

VDD(5V)

φA

φAB

φB

φBB

ENABLE

R01

FAULT1

FAULT2

R02

STK672-740B-E

9

13

17

12

10

15

RESETB

14

A

5

AB

7

3B

BB

1

2 phase stepping motor driver

R03

16

8

Vref 19

P.G2

2

6

P.G1

18

N.C

VCC

24V

+

C01

at least 100μF

P.GND

Precautions

[GND wiring]

• To reduce noise on the 5V system, be sure to place the GND of C01 in the circuit given above as close as possible to

Pin 2 and Pin 6 of the hybrid IC. Also, to achieve accurate current settings, be sure to connect Vref GND to the point

where P.G1 and P.G2 share a connection.

[Input pins]

• If VDD is being applied, use care that each input pin does not apply a negative voltage less than -0.3V to P.GND, and

do not apply a voltage greater than or equal to VDD voltage.

• Do not wire by connecting the circuit pattern on the P.C.B side to Pin 4, 11, or 18 on the N.C. shown in the internal

block diagram.

• Apply 2.5V high level input to pins 13, 17, 12, 10, 14, and 15.

• Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 13, 17, 12, 10, 14, and 15

are used as inputs, a 1 to 20kΩ pull-up resistor (to VDD) must be used.

At this time, use a device for the open collector driver that has output current specifications that pull the voltage down

to less than 0.8V at Low level (less than 0.8V at Low level when IOL=5mA).

[Current setting Vref]

If the motor current is temporarily reduced, the circuit given below (STK672-740B-E : IOH>0.3A) is recommended.

5V

5V

R01

Vref

R3

R02

R01

Vref

R3

R02

No. A1932-5/23

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