STK6005 Просмотр технического описания (PDF) - Unspecified
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Компоненты Описание
производитель
STK6005 Datasheet PDF : 36 Pages
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STK6005
SCL
INTN
RSTN
RefCLKI
RefCLKO
GPIO3-0
I I2C bus clock
O Interrupt request output (active low)
I Device reset input (active low)
I Crystal oscillator input
O Crystal oscillator output
I/O General purpose I/O and PWM
83
84
85
70
71
64-61
4.5 Power Pins
Name
VDD2
VSS2
VDD3
VSS3
VDD2P
VSS2P
AVDD
AVSS
P/G
Description
P Digital power supply for core cells
G Digital ground for core cells
P Digital power supply for I/O cells
G Digital ground for I/O cells
P Digital power supply for PLL
G Digital ground for PLL
P Analog power supply for PLL
G Analog ground for PLL
Pin No.
12,42,87,113
11,41,86,112
14,30,44,56,73, 128
13,28,43,55,72, 127
68
67
66
65
Note
2.5V
0V
3.3V
0V
2.5V
0V
2.5V
0V
4.6 Pin List
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin Name
PO_B[4]
PO_B[5]
PO_B[6]
PO_B[7]
PO_G[0]
PO_G[1]
PO_G[2]
PO_G[3]
PO_G[4]
PO_G[5]
VSS2
VDD2
VSS3
VDD3
PO_G[6]
PO_G[7]
PO_R[0]
PO_R[1]
PO_R[2]
PO_R[3]
PO_R[4]
PO_R[5]
PO_R[6]
PO_R[7]
PHS
PVS
PDE
VSS3
DCLK
VDD3
PE_B[0]
PE_B[1]
Pin No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin Name
PE_B[2]
PE_B[3]
PE_B[4]
PE_B[5]
PE_B[6]
PE_B[7]
PE_G[0]
PE_G[1]
VSS2
VDD2
VSS3
VDD3
PE_G[2]
PE_G[3]
PE_G[4]
PE_G[5]
PE_G[6]
PE_G[7]
PE_R[0]
PE_R[1]
PE_R[2]
PE_R[3]
VSS3
VDD3
PE_R[4]
PE_R[5]
PE_R[6]
PE_R[7]
GPIO0
GPIO1
GPIO2
GPIO3
Pin No.
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Pin Name
AVSS
AVDD
VSS2P
VDD2P
ExtPCLK
RefCLKI
RefCLKO
VSS3
VDD3
OVVS
OVHS
OVCLK
OVR
OVG
OVB
OVI
OVFB
SDA
SCL
INTN
RSTN
VSS2
VDD2
BIN[0]
BIN[1] / Cref
BIN[2] / LLC2
BIN[3] / Field
BIN[4] / Vsync
BIN[5] / Hsync
BIN[6] / Vref
BIN[7] / Href
GIN[0] / UV[0]
Pin No.
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Pin Name
GIN[1] / UV[1]
GIN[2] / UV[2]
GIN[3] / UV[3]
GIN[4] / UV[4]
GIN[5] / UV[5]
GIN[6] / UV[6]
GIN[7] / UV[7]
RIN[0] / Y[0]
RIN[1] / Y[1]
RIN[2] / Y[2]
RIN[3] / Y[3]
RIN[4] / Y[4]
RIN[5] / Y[5]
RIN[6] / Y[6]
RIN[7] / Y[7]
VSS2
VDD2
VCLK
HSI
CSync
VSI
VGAHS
ExtDE
Clamp
RGHS
MaskVS
PO_B[0]
PO_B[1]
PO_B[2]
PO_B[3]
VSS3
VDD3
9
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