STK6005 Просмотр технического описания (PDF) - Unspecified

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Компоненты Описание

производитель

STK6005

Flat Panel Scaler

Unspecified 

STK6005

4.1 ADC Interface

Name

RIN[7:0]

GIN[7:0]

BIN[7:0]

VCLK

HSI

CSync

VSI

VGAHS

ExtDE

Clamp

RGHS

MaskVS

I/O

Description

I Red input (RGB)

Y[7:0] input (YUV16)

YUV[7:0] input (YUV8)

I Green input (RGB) / UV[7:0] input (YUV16)

I Blue input (RGB) / YUV control input (YUV16)

Bit 7 : Href

Bit 6 : Vref

Bit 5 : Hsync

Bit 4 : Vsync

Bit 3 : Field

Bit 2 : LLC2

Bit 1 : Cref

I Video input clock / YUV LLC clock

I RGB horizontal sync input (after ADC)

I Composite sync input (from SOG)

I RGB vertical sync input

I Original VGA H-Sync input (before ADC)

I External DE input

O Clamp signal to ADC

O To regenerate an H-Sync output

O Coast signal to ADC

Pin No.

111-104

Note

103-96

95-88

114

115

116

117

118

119

120

121

122

4.2 Panel Interface

Name

PE_R[7:0]

PE_G[7:0]

PE_B[7:0]

PO_R[7:0]

PO_G[7:0]

PO_B[7:0]

DCLK

PHS

PVS

PDE

ExtPCLK

I/O

Description

O Even port (port A) red output

O Even port (port A) green output

O Even port (port A) blue output

O Odd port (port B) red output

O Odd port (port B) green output

O Odd port (port B) blue output

O Panel data clock output

O Panel H-Sync output

O Panel V-Sync output

O Panel data enable output

I External panel clock input

Pin No.

60-57, 54-51

50-45, 40-39

38-31

24-17

16-15, 10-5

4-1, 126-123

29

25

26

27

69

Note

4.3 OSD Interface

Name

OVVS

OVHS

OVCLK

OVR

OVG

OVB

OVI

OVFB

I/O

Description

O Overlay V-Sync output

O Overlay H-Sync output

O Overlay clock output

I Overlay red input

I Overlay green input

I Overlay blue input

I Overlay intensity input

I Overlay color enable

Pin No.

74

75

76

77

78

79

80

81

Note

4.4 Micro-Controller Interface

Name

SDA

I/O

I/O I2C bus data

Description

8

Pin No.

82

Note

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