STK6005 Просмотр технического описания (PDF) - Unspecified

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Компоненты Описание

производитель

STK6005

Flat Panel Scaler

Unspecified 

STK6005

0x3C

0x3D

0x3E

[3]

[2:0]

[7]

[6]

[5:0]

[7:0]

EnFilt

FiltType[2:0]

EnSyncH

EnSyncV

DlyLine[5:0]

DlyPxl[7:0]

0

0x4

0

1

0x03

0x40

R/W 1 : enable scaling

Filter type 000 ~ 101

R/W 00 : free-run mode

01 : panel timing sync to input VS

1x : panel timing sync to input HS

panel to input timing sync point line delay (>=1)

R/W panel to input timing sync point pixel delay * 8 (>=1)

6.4 Panel Output Control

Address Bit

Name

0x40 [7:0] GainR[7:0]

0x41 [7:0] GainG[7:0]

0x42 [7:0] GainB[7:0]

0x43 [7:0] DC_R[7:0]

0x44 [7:0] DC_G[7:0]

0x45 [7:0] DC_B[7:0]

0x46 [7:0] uWrGmaA

0x47 [7:0] uWrGmaD

0x48 [7:0] BGColurR[7:0]

0x49 [7:0] BGColurG[7:0]

0x4A [7:0] BGColurB[7:0]

0x4B [6]

GmaWEB

[5]

GmaWEG

[4]

GmaWER

[3]

EnGamma

[2]

EnFRC

[1:0]

DithType

0x4C

0x4D

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

[6]

[5]

[4]

[3]

[2:0]

Mute

Mute1

SPO

EnTriPO

EnDCLK

EnPCtrl

EnPDOB

EnPDOA

SetPDE

SetPVS

SetPHS

SetDCLK

DlyDCLK

Initial R/W

Description

0x80 R/W Panel output red / green / blue contrast adjustment

0x80 R/W Range : 0x00 ~ 0x80 ~ 0xFF = dark ~ normal ~ bright

0x80 R/W

0x00 R/W Panel output red / green / blue brightness adjustment

0x00 R/W Range : 0x80 ~ 0x00 ~ 0x7F = dark ~ normal ~ bright

0x00 R/W

W To set address of gamma table to write

W To set data to write into gamma table

0x00 R/W Panel background color red

0x00 R/W Panel background color green

0x00 R/W Panel background color blue

1 R/W Modification enable of color blue gamma table

1

Modification enable of color green gamma table

1

Modification enable of color red gamma table

0

1 = to enable gamma correlation

1

1 = to enable dynamic dithering

0x0

Dithering mode :

00 / 01 / 10 / 11 => OFF / 8 bits / 7 bits / 6 bits

0 R/W 1 : force output panel background color

0

1 : force bit [1:0] output low

0

0/1 : dual / single ports panel output

1

0/1 : output low / tri-state when panel output is disabled

0

1 : enable DCLK output

0

1 : enable PHS / PVS / PDE output

0

1 : enable port B (odd port) output

0

1 : enable port A (even port) output

0 R/W 0/1 : to set PDE output polarity to positive / negative

0

0/1 : to set PVS output polarity to positive / negative

0

0/1 : to set PHS output polarity to positive / negative

0

0/1 : to set DCLK output polarity to positive / negative

0x0

To adjust DCLK output delay to 0 ~ 8.4ns, 1.2ns per step

28

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