STK6005 Просмотр технического описания (PDF) - Unspecified
Номер в каталоге
Компоненты Описание
производитель
STK6005 Datasheet PDF : 36 Pages
| |||
STK6005
0x1D
0x1E
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7:0]
SelDE
EnYUV
SetVref
SetHref
SetCref
SetField
YUV16
SelLLC2
VSDelay
0
0
0
0
0
0
0
0
0x04
R/W 0/1 : to select register setting / ExtDE as display active
1 : to select a YUV input
0/1 : to set Vref polarity to positive / negative
0/1 : to set Href polarity to positive / negative
0/1 : to set Cref polarity to positive / negative
0/1 : to set Field (Odd) polarity to positive / negative
0/1 : video format is a 8-bit (CCIR 656) / 16-bit format.
1 : to select LLC2 as input clock
R/W Delay of internal Vsync (* 8 input clocks)
6.2 Panel Window Control
Address Bit
Name
0x20 [7:0] PHDE1[7:0]
0x21 [3:0] PHDE1[11:8]
0x22 [7:0] PHDE2[7:0]
0x23 [3:0] PHDE2[11:8]
0x24 [7:0] PHXDE1[7:0]
0x25 [3:0] PHXDE1[11:8]
0x26 [7:0] PHXDE2[7:0]
0x27 [3:0] PHXDE2[11:8]
0x28 [7:0]
PHT[7:0]
0x29 [3:0] PHT[11:8]
0x2A [7:0] PHSW[7:0]
0x2B [7:0] PVSW[7:0]
0x2C [7:0] PVDE1[7:0]
0x2D [2:0] PVDE1[10:8]
0x2E [7:0] PVDE2[7:0]
0x2F [2:0] PVDE2[10:8]
0x30 [7:0] PVXDE1[7:0]
0x31 [2:0] PVXDE1[10:8]
0x32 [7:0] PVXDE2[7:0]
0x33 [2:0] PVXDE2[10:8]
0x34 [7:0]
PVT[7:0]
0x35 [2:0] PVT[10:8]
Initial R/W
Description
0x28 R/W Panel horizontal DE start position (# of PCLKs)
0x1 R/W
0x28 R/W Panel horizontal DE end position (# of PCLKs)
0x5 R/W
0x28 R/W Panel horizontal image start position (# of PCLKs)
0x1 R/W
0x28 R/W Panel horizontal image end position (# of PCLKs)
0x5 R/W
0x40 R/W Panel horizontal total (# of PCLKs)
0x5 R/W set PHT = 0xFFF if EnSyncH = 1
0x88 R/W Panel horizontal sync width (# of PCLKs)
0x06 R/W Panel vertical sync width (# of lines)
0x23 R/W Panel vertical DE start position (# of lines)
0x0 R/W
0x23 R/W Panel vertical DE end position (# of lines)
0x3 R/W
0x23 R/W Panel vertical image start position (# of lines)
0x0 R/W
0x23 R/W Panel vertical image end position (# of lines)
0x3 R/W
0x26 R/W Panel vertical total (# of lines)
0x3 R/W set PVT = 0x7FF if EnSyncH/V = 1
6.3 Scaling Control
Address Bit
Name
0x36 [7:0]
HSR[7:0]
0x37 [7:0] HSR[15:8]
0x38 [7:0]
VSR[7:0]
0x39 [7:0] VSR[15:8]
0x3A [7:0] EmPHT[7:0]
0x3B [7:0] EmPHT[15:8]
Initial R/W
Description
0x00 R/W Horizontal expansion ratio = (INres / OUTres) *32768
0x80 R/W
0x00 R/W Vertical expansion ratio = (INres / OUTres) * 32768
0x80 R/W
0x00 R/W Emulate PHT by input clocks = (Panel H period / input
0x54 R/W clock period) * 16
27
Back to Contents Table
Share Link: 