STB4395 Просмотр технического описания (PDF) - STMicroelectronics

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STB4395

CT2 RECEIVER/TRANSMITTER

STMicroelectronics 

STB4395

3 - FUNCTIONAL DESCRIPTION

Figure 1 is a simplified block diagram of the circuit.

It shows the key on-chip and off-chip functional

blocks and signal paths. For illustration purposes

frequencies have been added representing the

situation when receiving or transmitting a particular

CT2 channel.

3.1 - Receiver

The receive signal enters the STB4395 via an input

SAW filter (866 MHZ for CT2 in Europe). The RF

filter changes the input signal from a single ended

to a balanced signal, after which the signal passes

through the LNA, first mixer, and mixer buffer. The

mixer is driven by the channel VCO, which is in turn

controlled by the synthesizer.

The signal path continues via the first IF SAW

(150.4MHz), IF amplifier to the second mixer. The

second mixer stage mixes down to 1.7MHz, and

via an external LC IF filter, is passed to the second

IF amplifier, where the main system gain takes

place. The RSSI output is available from this

point.The signal is then demodulated and sliced

into a data stream which is the binary digital output

available to the base band chip.

The channel selection is provided by the two exter-

nal filters: the first IF SAW and a second IF 2-pole

LC filter.

3.2 - Transmitter

The chip accepts 72Kbits/s data in an I/Q format.

The I/Q inputs pass via the I/Q modulator to the

TX mixer. The TX mixer is driven by the same

channel VCO as the receive first mixer.

4 - ABSOLUTE MAXIMUM RATINGS

Symbol

VP-VN

VP - VIN

VP - VIN

VIN - VN

VP- VOUT

VN - VOUT

VRFO

Tstg

Toper

Parameter

Power Supply Voltage

Voltages on Input (except SYNCLK)

Voltage on Input (SYNCLK)

Voltages on Input

Voltages on Output

Voltages on Output

Voltage Out of RF or NRF in TX

Storage Temperature

Operating Temperature

The on-off ramp of the transmit PA.is controlled via

an external capacitor to give minimum spurious

responses when switching on and off.

The PA output power can be switched from full

power to -3dBm by the channel select control

signal (bit LO of the 16bits serial word PRGD, see

table, paragraph 1.4).

3.3 - Channel Select Control Logic

All channel phase locked loops and oscillators are

included on chip. The channel control synthesizer

is controlled externally via a 3 wire interface.

The Reference clock input of 14.4 MHz is divided

using preset counters to set the phase detector

/charge pump loops for the synthesizer/channel

select VCO, the second receiver VCO, and the I/Q

transmit VCO. The phase detector inputs for the

fixed frequency VCO’s arevia pre set dividers also.

The channel select control and Transmit PA control

is via a 16 bit serial word, which is generated by the

system controller. 15 bits of this serial word are

used for the channel information, and 1 bit is used

to setthe output power of the transmit PA. Theword

length is sufficient to give full channel coverage

over the range from 800 to 1000MHz with integer

multiples of 50KHz. The section ”system clock

input” gives a detailed description.

Not shown in the diagram are the voltage regula-

tors for the receive LNA/first mixer, Transmit PA, TX

mixer and the remainder of the circuit.There are 6

internal voltage regulators to ensure the minimum

of mutual interference.

Value

Unit

7.0

V

5.9

V

3.0

V

7.0

V

7.0

V

7.0

V

3.5

VPP

125

oC

40

oC

8/16

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