ST78C36 Просмотр технического описания (PDF) - Exar Corporation
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ST78C36 Datasheet PDF : 27 Pages
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REV. 5.1.0
ST78C36/36A
ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO
PIN DESCRIPTION
NAME
44-PLCC 64-LQFP
TYPE
PIN #
PIN#
DESCRIPTION
DATA BUS INTERFACE
A10
29
36
I Address Select Lines. A10 places the ECP control/status/data ports at
A2
39
46
0x400 offset from the -CS decoded address.
A1
41
53
A0
40
52
D7
9
5
I/O Data bus. Bi-directional data port.
D6
10
6
D5
11
7
D4
12
8
D3
13
9
D2
14
10
D1
15
11
D0
16
12
-IOR
43
55
I Active low AT bus I/O Read strobe.
-IOW
42
54
I
-CS
22
24
I Chip select (active LOW). A LOW at this pin enables the parallel port /
CPU data transfer operation.
IOCHRDY
18
19
O I/O Channel ready (internal pull-up / three stated active HIGH). This pin
goes low when the device requires addition clock cycles for read and
write.
-IRQ9
-IRQ7
-IRQ5
-
14
O Interrupt Request Lines (three stated active low).
19
20
-
18
AEN
17
13
I DMA address enable (active HIGH). When this line is HIGH, the DMA
controller has control of the address bus.
DRQ3
DRQ2
DRQ1
7
3
O Active high AT bus DMA ReQuest for channels 3, 2 and 1 (internal pull-
-
63
-
51
down three stated active HIGH). A request is generated by bringing a
DRQx line to a HIGH level. A DRQx line is held HIGH until the corre-
sponding DMA acknowledge “DACKx*” line goes LOW.
-DACK3
8
-DACK2
-
4
I DMA Acknowledge signals for channels 3, 2 and 1 (internal pull-up /three
2
stated active low).
-DACK1
-
47
TC
6
62
I Terminal Count (active HIGH). The ST78C36 terminates the DMA channel
when a HIGH pulse is detected.
3
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