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ST78C36

ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO

Exar Corporation 

ST78C36/36A

ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO

REV. 5.1.0

ECR Bit-2:

When low, this bit (ServiceIntr) enables a pulsed interrupt and enables DMA requests (if bit-3 is set). If the

enabled interrupt occurs, this bit is automatically returned to a high. The interrupt conditions are:

ECR Bit-3 = DMA

DCR Bit-5 = DIRection

TABLE 3: DMA CONDITION

DMA

DIR

CONDITION

0

0 8 empty bytes in the FIFO

0

1 8 filled bytes in the FIFO

1

X DMA Terminal Count (TC).

ECR BIT-3:

This bit disables DMA when set low. When set high, a low on ServiceIntr will enable DMA requests.

0 = DMA disabled, DRQx pin is three-stated.

1 = DMA enabled

ECR Bit-4:

When low, this bit (-ErrIntrEn) enables a pulsed interrupt if -ERROR (-Fault) is low. The interrupt is only

enabled in ECP mode.

ECR Bits 7-5:

This field can be set to any value if the current value is 000 or 001. If the current value is not 000 or 001, then

the field can only be written to 000 or 001. The modes are defined as:

TABLE 4: DESCRIPTION OF PARALLEL PORT MODES

MODE

NAME

DESCRIPTION

000

SPP

Standard Centronics, output only. DCR bit-5 is forced to "0".

001

PS2

Bi-directional PS/2 parallel port. FIFO is disabled

010

PPF

FIFOed, output only. DCR Bit-5 is forced to “0”.

011

ECP

ECP FIFOed port with RLE de-compression. FIFO direction is controlled by DCR Bit-5.

100

EPP

EPP mode.

101

-

Reserved.

110

TST

FIFO test mode. FIFO is accessible via TFIFO register.

111

CFG

Configuration A/B register enable.

10

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