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REV. 5.0.1
ST78C36/36A
ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO
3.12 EXTENDED CONTROL REGISTER ( ECR )
The Extended Control Register has a system RESET state of 10010101. The significance of the bits is defined
by the ECP specification as:
ECR Bit-0:
This read-only bit returns FIFO empty status (FIFO-E) and is forced high unless PPF, ECP, or TST mode is
selected.
0 = At least one byte of data contains in the FIFO.
1 = FIFO is empty.
ECR Bit-1:
This read-only bit returns FIFO full status (FIFO-F) and is forced low unless PPF, ECP, or TST mode is
selected.
0 = At least one empty location is available in the FIFO.
1 = FIFO is full.
ECR Bit-2:
When low, this bit (ServiceIntr) enables a pulsed interrupt and enables DMA requests (if bit-3 is set). If the
enabled interrupt occurs, this bit is automatically returned to a high. The interrupt conditions are:
ECR Bit-3 = DMA
DCR Bit-5 = DIRection
TABLE 3: DMA CONDITION
DMA
DIR
CONDITION
0
0 8 empty bytes in the FIFO
0
1 8 filled bytes in the FIFO
1
X DMA Terminal Count (TC).
ECR BIT-3:
This bit disables DMA when set low. When set high, a low on ServiceIntr will enable DMA requests.
0 = DMA disabled, DRQx pin is three-stated.
1 = DMA enabled
ECR Bit-4:
When low, this bit (-ErrIntrEn) enables a pulsed interrupt if -ERROR (-Fault) is low. The interrupt is only
enabled in ECP mode.
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