ST7036-0A Просмотр технического описания (PDF) - Sitronix Technology Co., Ltd.
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ST7036-0A Datasheet PDF : 70 Pages
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ST7036
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
not acknowledge
acknowledge
1
2
8
9
S
START
condition
clock pulse for
acknowledgement
Fig .4 Acknowledgement on the IIC Interface
I2C Interface protocol
The ST7036 supports command, data write addressed slaves on the bus.
Before any data is transmitted on the I2C Interface, the device, which should respond, is addressed first. Four 7-bit slave
addresses (0111100 to 0111111) are reserved for the ST7036. The R/W is assigned to 0 for Write only.
The I2C Interface protocol is illustrated in Fig.5.
The sequence is initiated with a START condition (S) from the I2C Interface master, which is followed by the slave address.
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C Interface transfer. After
acknowledgement, one or more command words follow which define the status of the addressed slaves.
A command word consists of a control byte, which defines Co and RS, plus a data byte.
The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a
cleared Co bit, only data bytes will follow. The state of the RS bit defines whether the data byte is interpreted as a command
or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte,
depending on the RS bit setting; either a series of display data bytes or command data bytes may follow. If the RS bit is set
to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is
automatically updated and the data is directed to the intended ST7036i device. If the RS bit of the last control byte is set to
logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received
commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I2C
INTERFACE-bus master issues a STOP condition (P).
Write mode
acknowledgement
from ST7036i
acknowledgement
from ST7036i
acknowledgement
from ST7036i
acknowledgement
from ST7036i
acknowledgement
from ST7036i
S
0
1
1
1
1
1
0
0
A
1
R
S
slave address R/W
Co
control byte A
data byte
2n>=0 bytes
command word
A
0
R
S
control byte
1 byte
Co
A
data byte
AP
n>=0 bytes
MSB.......................LSB
R
01111 10 /
W
CR
oS
0
0
0
0
0
0
DDDDDDDD
76543210
slave address
control byte
data byte
Co 0
1
Fig .5 IIC Interface protocol
Last control byte to be sent. Only a stream of data bytes is allowed to follow.
This stream may only be terminated by a STOP condition.
Another control byte will follow the data byte unless a STOP condition is received.
During write operation, two 8-bit registers are used. One is data register (DR), the other is instruction
register(IR).
The data register(DR) is used as temporary data storage place for being written into DDRAM/CGRAM/ICON
RAM, target RAM is selected by RAM address setting instruction. Each internal operation, writing into RAM, is
done automatically. So to speak, after MPU writes data to DR, the data in DR is transferred into
DDRAM/CGRAM/ICON RAM automatically.
V1.7a
16/70
2007/10/17
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