ST7036-0A Просмотр технического описания (PDF) - Sitronix Technology Co., Ltd.

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ST7036-0A

Dot Matrix LCD Controller/Driver

Sitronix Technology Co., Ltd. 

ST7036

Function Description

System Interface

This chip has all four kinds of interface type with MPU: 4-bit bus, 8-bit bus, serial and fast I2C interface. 4-bit bus

or 8-bit bus is selected by DL bit in the instruction register.

During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction

register(IR).

The data register(DR) is used as temporary data storage place for being written into or read from

DDRAM/CGRAM/ICON RAM, target RAM is selected by RAM address setting instruction. Each internal

operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the

data in the next DDRAM/CGRAM/ICON RAM address is transferred into DR automatically. Also after MPU writes

data to DR, the data in DR is transferred into DDRAM/CGRAM/ICON RAM automatically.

The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to

read instruction data.

To select register, use RS input pin in 4-bit/8-bit bus mode.

RS R/W

Operation

L L Instruction Write operation (MPU writes Instruction code into IR)

L H Read Busy Flag(DB7) and address counter (DB0 ~ DB6)

H L Data Write operation (MPU writes data into DR)

H H Data Read operation (MPU reads data from DR)

I2C interface

Table 1. Various kinds of operations according to RS and R/W bits.

It just only could write Data or Instruction to ST7036 by the IIC Interface.

It could not read Data or Instruction from ST7036 (except Acknowledge signal).

SCL: serial clock input

SDA_IN: serial data input

SDA_OUT: acknowledge response output

Slaver address could set from “0111100” to “0111111”.

The I2C interface send RAM data and executes the commands sent via the I2C Interface. It could send data in to the RAM.

The I2C Interface is two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA)

and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be

initiated only when the bus is not busy.

BIT TRANSFER

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of

the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated

in Fig.1.

START AND STOP CONDITIONS

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock

is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined

as the STOP condition (P). The START and STOP conditions are illustrated in Fig.2.

SYSTEM CONFIGURATION

The system configuration is illustrated in Fig.3.

· Transmitter: the device, which sends the data to the bus

· Master: the device, which initiates a transfer, generates clock signals and terminates a transfer

· Slave: the device addressed by a master

· Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message

V1.7a

14/70

2007/10/17

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