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ST10F167

16-BIT MCU WITH 128KBYTE FLASH MEMORY

STMicroelectronics 

ST10F167

16-BIT MCU WITH 128KBYTE FLASH MEMORY

s HIGH PERFORMANCE CPU

– 16-BIT CPU WITH 4-STAGE PIPELINE.

– 16-BIT CPU WITH 4 STAGE PIPELINE

– 100NS INSTRUCTION CYCLE TIME AT 20MHz

CPU CLOCK

– 500NS MULTIPLICATION (16*16 BIT)

– 1µS DIVISION (32/16 BIT)

– ENHANCED BOOLEAN BIT MANIPULATION

FACILITIES

– ADDITIONAL INSTRUCTIONS TO SUPPORT HLL

AND OPERATING SYSTEMS

– SINGLE-CYCLE CONTEXT SWITCHING SUPPORT

s MEMORY ORGANIZATION

– 2K BYTE ON-CHIP INTERNAL RAM

– 2K BYTE ON-CHIP EXTENSION RAM

– 128K BYTE ON-CHIP FLASH MEMORY

– FLASH WITH 4 INDEPENDENTLY ERASABLE BANKS

s FAST AND FLEXIBLE BUS

– PROGRAMMABLEEXTERNALBUS CHARACTER-

ISTICS FOR DIFFERENT ADDRESS RANGES

– 8-BIT OR 16-BIT EXTERNAL DATA BUS.

– MULTIPLEXED OR DE-MULTIPLEXED EXTER-

NAL ADDRESS/DATA BUSES

– FIVE PROGRAMMABLECHIP-SELECT SIGNALS.

– HOLD AND HOLD-ACKNOWLEDGE BUS ARBI-

TRATION SUPPORT

s FAIL-SAFE PROTECTION

– PROGRAMMABLE WATCHDOG TIMER

s ON-CHIP CAN 2.0B INTERFACE

s ON-CHIP BOOTSTRAP LOADER

s INTERRUPT

– 8-CHANNEL PEC FOR SINGLE CYCLE, INTER-

RUPT DRIVEN DATA TRANSFER

– 16-PRIORITY-LEVEL INTERRUPT SYSTEM WITH

56 SOURCES, SAMPLE-RATE DOWN TO 50ns

s TIMERS

– TWO MULTI-FUNCTIONAL GENERAL-PURPOSE

TIMER UNITS WITH 5 TIMERS

– TWO 16-BIT CAPTURE/COMPARE UNITS

s A/D CONVERTER

– 16-CHANNEL 10-BIT 9.7µS CONVERSION TIME

s CLOCK GENERATION

– ON-CHIP PLL.

– DIRECT CLOCK INPUT

s UP TO 111 GENERAL PURPOSE I/O LINES

– PROGRAMMABLE THRESHOLD (HYSTERESIS)

PQFP144 (28 x 28 mm)

(Plastic Quad Flat Pack)

s IDLE AND POWER DOWN MODES

– IDLE CURRENT <70mA

– POWER DOWN SUPPLY CURRENT <100µA.

s 4-CHANNEL PWM UNIT

s SERIAL CHANNELS

– SYNCHRONOUS/ASYNCH SERIAL CHANNEL.

– HIGH SPEED SYNCHRONOUS CHANNEL

s ELECTRICAL CHARACTERISTICS

– POWER - 5V ± 10%

s DEVELOPMENT SUPPORT

– C-COMPILERS, MACRO-ASSEMBLER PACKAGES,

EMULATORS, EVALUATION BOARDS, HLL-DE-

BUGGERS, SIMULATORS, LOGIC ANALYZER DIS-

ASSEMBLERS, PROGRAMMING BOARDS

s PACKAGE OPTION

– 144-PIN PQFP PACKAGE

XRAM

CPU-Core

PE C

Interrupt Controller

Internal

RAM

W dog

BRG BRG

P.6

P.5

P.3

P.7

P.8

July 1999

This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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