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ST10F167 Просмотр технического описания (PDF) - STMicroelectronics

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ST10F167
ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST10F167 Datasheet PDF : 61 Pages
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ST10F167
IV - MEMORY ORGANIZATION
The memory space of the ST10F167 is configured
in a Von-Neumann architecture. Code memory,
data memory, registers and I/O ports are orga-
nized within the same linear address space of
16M Byte. The entire memory space can be
accessed Bytewise or Wordwise. Particular por-
tions of the on-chip memory have additionally
been made directly bit addressable.
The ST10F167 provides 128K Byte of on-chip
flash memory.
2K Byte of on-chip Internal RAM stores user
defined variables for the system stack, general
purpose register banks and even for code. A reg-
ister bank can consist of up to 16 Wordwide (R0 to
R15) and/or Bytewide (RL0, RH0, , RL7, RH7)
so-called General Purpose Registers (GPRs).
1024 Byte (2 * 512 Byte) of the address space are
reserved for the Special Function Register areas
(SFR space and ESFR space). SFRs are Word-
wide registers which are used for controlling and
monitoring functions of the different on-chip units.
Unused SFR addresses are reserved for other/
future members of the ST10 family.
2K Byte of on-chip Extension RAM (XRAM) are
provided to store user data, user stacks or code.
The XRAM is accessed like external memory and
cannot be used for the system stack or register
banks, and is not bit-addressable. The XRAM
allows 16-bit accesses with maximum speed.
In order to meet the needs of designs where more
memory is required than is provided on chip, up to
16M Byte of external RAM and/or ROM can be
connected to the microcontroller.
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