SST32HF1682 Просмотр технического описания (PDF) - Silicon Storage Technology
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SST32HF1682 Datasheet PDF : 36 Pages
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Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1642 / SST32HF1682 / SST32HF3242 / SST32HF3282
SST32HF1622C / SST32HF1642C / SST32HF3242C
Preliminary Specifications
Flash Word-Program Operation
The flash memory bank of the SST32HFx2/x2C devices is
programmed on a word-by-word basis. Before Program
operations, the memory must be erased first. The Program
operation consists of three steps. The first step is the three-
byte load sequence for Software Data Protection. The sec-
ond step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either BEF# or WE#, whichever occurs last.
The data is latched on the rising edge of either BEF# or
WE#, whichever occurs last. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or BEF#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed, within 10
µs. See Figures 7 and 8 for WE# and BEF# controlled Pro-
gram operation timing diagrams and Figure 21 for flow-
charts. During the Program operation, the only valid flash
Read operations are Data# Polling and Toggle Bit. During
the internal Program operation, the host is free to perform
additional tasks. During the command sequence, WP#
should be statically held high or low. Any SDP commands
loaded during the internal Program operation will be
ignored.
Flash Sector/Block-Erase Operation
The Flash Sector/Block-Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST32HFx2/x2C offer both Sector-Erase
and Block-Erase mode. The sector architecture is based
on uniform sector size of 2 KWord. The Block-Erase mode
is based on uniform block size of 32 KWord. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The address lines
AMS-A11 are used to determine the sector address. The
Block-Erase operation is initiated by executing a six-byte
command sequence with Block-Erase command (50H)
and block address (BA) in the last bus cycle. The address
lines AMS-A15 are used to determine the block address.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
The End-of-Erase operation can be determined using
either Data# Polling or Toggle Bit methods. See Figures 12
and 13 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored, WP#
should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ2 toggling and DQ6 at “1”. While in Erase-Suspend
mode, a Word-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has
been suspended the system must issue Erase Resume
command. The operation is executed by issuing one byte
command sequence with Erase Resume command (30H)
at any address in the last Byte sequence.
Flash Chip-Erase Operation
The SST32HFx2/x2C provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or BEF#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 6 for the command sequence, Figure 10 for tim-
ing diagram, and Figure 25 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored.
Write Operation Status Detection
The SST32HFx2/x2C provide two software means to
detect the completion of a write (Program or Erase) cycle,
in order to optimize the system Write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Program or Erase operation.
©2005 Silicon Storage Technology, Inc.
3
S71253-03-000
5/05
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