SP7800 Просмотр технического описания (PDF) - Signal Processing Technologies
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SP7800 Datasheet PDF : 13 Pages
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AC DYNAMIC TIMING DATA
SYMBOL/PARAMETER
tW
tDBC
tB
tAP
∆tAP
tC
tDBE
tDB
tA
tA + tC
tHDR
tS
tH
tDD
R/C Pulse Width
BUSY delay from R/C
BUSY LOW
Aperture Delay
Aperture Jitter
Conversion Time
BUSY from End of Conversion
BUSY Delay after Data Valid
Acquisition Time
Throughput Time
Valid Data Held After R/C LOW
CS or HBE LOW before R/C Falls
CS or HBE LOW after R/C Falls
Data Valid from CS LOW, R/C HIGH, and HBE
in Desired State (Load = 100pF)
tHL
Delay to Hi-Z State after R/C Falls or
CS Rises (3KΩ Pullup or Pulldown
All parameters Guaranteed By Design
MIN
TYP
MAX
UNITS
40
10
ns
80
150
ns
2.47
2.7
µs
13
ns
150
ps, rms
2.5
2.70
µs
100
ns
25
75
200
ns
130
300
ns
3.0
µs
20
50
ns
25
5
ns
25
0
ns
65
150
ns
50
150
ns
Naturally, transients on the analog input signal are to
be avoided, especially at times within ±20ns of R/C
going LOW, when they may be trapped as part of the
charge on the capacitor array. This requires careful
layout of the circuit in front of the SP7800A.
Finally, in multiplexed systems, the timing relative to
when the multiplexer is switched may affect the
analog performance of the system. In most applica-
tions, the multiplexer can be switched as soon as R/C
goes LOW (with appropriate delays), but this may
affect the conversion if the switched signal shows
glitches or significant ringing at the SP7800A input.
Whenever possible, it is safer to wait until the conver-
sion is completed before switching and multiplexer.
The extremely fast acquisition time and conversion
time of the SP7800A make this practical in many
applications.
CS or
HBE
tS
tH
R/C
tW
BUSY
tDBC
Data
BUS
Data Valid
Figure 7. Conversion Start Timing
Hi-Z State
tHDR and tHL
SP7800ADS/02
SP7800A 12-Bit 3µs Sampling A/D Converter
10
© Copyright 2000 Sipex Corporation
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