SP705CP Просмотр технического описания (PDF) - Signal Processing Technologies

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SP705CP

Low Power Microprocessor Supervisory Circuits

Signal Processing Technologies 

+5V

VCC = +5V

TA = +25 C

PFI

PFO

+1.25V

30pF

1KΩ

Figure 4A. Power-Fail Comparator De-assertion

Response Time.

Figure 4B. Circuit for the Power-Fail Comparator De-

assertion Response Time.

VCC = +5V

TA = +25 C

PFI

+5V

PFO

1KΩ

+1.25V

30pF

Figure 5A. Power-Fail Comparator Assertion Response

Time.

Figure 5B. Circuit for the Power-Fail Comparator

Assertion Response Time.

Figure 6A. SP705/707 RESET Output Voltage vs.

Supply Voltage.

VCC

TA = +25oC

VCC

2KΩ

RESET

RESET

GND

330pF

Figure 6B. Circuit for the SP705/707 RESET Output

Voltage vs. Supply Voltage.

SP705DS/09

SP705 Low Power Microprocessor Supervisory Circuits

6

© Copyright 2000 Sipex Corporation

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