CA3224E(1996) Просмотр технического описания (PDF) - Intersil
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CA3224E Datasheet PDF : 6 Pages
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CA3224E
Test Circuit
1
VIN1
2
VIN2
3
0.047
µF
4
+10V
VBIAS
3.65K
22
B
21 S1 A 0.12µF
20
VOUT1
B 3.65K
19
S1 A 0.12µF
VIN3
0.047
µF
5
18
6
17
CA3224E
VOUT2
B 3.65K
S1 A 0.12µF
VERTICAL
INPUT
7
0.047
µF 8
9
16
47µF
15
+
VOUT3
+20V
14
3.32K
HORIZONTAL
INPUT
1.50K
1.0K
+10V
B
10
13
20K
S2 A
11
12
1.5K
Device Description and Operation
(See Figures 1, 2, 4 and 5)
During the vertical retrace interval, 13 horizontal sync pulses
are counted. On the 14th sync pulse the auto-bias pulse out-
put goes high. This is used to set the RGB drive of the com-
panion chroma/luma circuit to black level. The auto-bias pulse
stays high for 7 horizontal periods during the auto-bias cycle.
On the 15th horizontal sync pulse, the internal logic initiates
the setup interval. During the setup interval, the cathode cur-
rent is increased to a reference value (A in Figure 5) through
the action of the grid pulse. The cathode current causes a
voltage drop across RS. This voltage drop, together with the
program pulse output results in a reference voltage at VS
(summing point) which causes capacitor C1 to charge to a
voltage proportional to the reference cathode current. The
setup interval lasts for 3 horizontal periods.
On the 18th horizontal sync pulse the grid pulse output goes
high, which through the grid pulse amplifier/inverter, causes
the cathode current to decrease. The decrease in cathode
current results in a positive recovered voltage pulse with
respect to the setup reference level at the VS summing point.
The positive recovered voltage pulse is summed with a nega-
tive voltage pulse caused by the program pulse output going
low (cutting off Diode D1 and switching in resistors R1 and
R2). Any difference between the positive and negative pulses
is fed through capacitor C1 to the transconductance amplifier.
The difference signal is amplified in the transconductance
amplifier and charges the hold capacitor C2, which, through
the buffer amplifier, adjusts the bias on the driver circuit.
Components RS, R1, and R2 must be chosen such that the
program pulse and the recovered pulse just cancel at the
desired cathode cutoff level.
CHAN FREQ
1 IN COMP
23
HOLD CHAN CHAN FREQ
CAPACITOR 1 OUT 2 IN COMP
21
20
4
5
HOLD
CAPACITOR
19
CHAN CHAN FREQ
2 OUT 3 IN COMP
18
6
7
HOLD
CAPACITOR
17
CHAN
3 OUT
16
AMPLIFER
NO. 1
1
-
2
+
3
gM
BUFFER
AMP
x1
AMPLIFER
NO. 2
-
12
+
gM
3
BUFFER
AMP
x1
AMPLIFER
NO. 3
1
-
2
+
gM
3
BUFFER
AMP
x1
VREF
MODE
SWITCH
BIAS
LOGIC
1
GND
MODE SWITCH
1
2
3
9
GND
STATE
SET-UP
SENSE
OPEN
22
VCC
15
VREF
BYPASS
8
VERT
IN
10
HORIZ
IN
11
GRID
PULSE
OUT
12
PROG
PULSE
OUT
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
13
AUTO
BIAS
PULSE
OUT
14
AUTO
BIAS
LEVEL
ADJUST
8-58
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