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UDA1342TS Просмотр технического описания (PDF) - Philips Electronics

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производитель
UDA1342TS
Philips
Philips Electronics Philips
UDA1342TS Datasheet PDF : 44 Pages
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Philips Semiconductors
Audio CODEC
Preliminary specification
UDA1342TS
8.11 Sampling speed
The UDA1342TS operates with sample frequencies from
16 to 110 kHz. This range holds for the CODEC as a
whole. The DAC part can be configured in the L3-bus and
I2C-bus mode to accept 2 times and even 4 times the data
speed (e.g. fs is 96 or 192 kHz), but in these modes not all
of the features can be used.
Some examples of the input oversampling rate settings
are shown in Table 4.
Important: in the double speed mode an input signal of
0 dB is allowed, but in the quad speed mode the input
signal must be limited to 6 dB to prevent the system from
clipping.
Table 4 Examples of the input oversampling rate settings
SYSTEM CLOCK
12.288 MHz (256 × 48 kHz)
22.5792 MHz (512 × 44.1 kHz)
33.8688 MHz (768 × 44.1 kHz)
SYSTEM
CLOCK
FREQUENCY
SETTING
256fs
512fs
256fs
768fs
384fs
SAMPLING INPUT OVER-
FREQUENCY SAMPLING
(kHz)
RATE
FEATURES SUPPORTED
48
96
192
44.1
88.2
176.4
44.1
88.2
176.4
single speed
double speed
quad speed
single speed
single speed
double speed
single speed
single speed
double speed
all
only master volume and mute
no features
all
all
only master volume and mute
all
all
only master volume and mute
8.12 Power-on reset
The UDA1342TS has an internal Power-on reset circuit
(see Fig.7) which resets the test control block. All the
digital sound processing features and the system
controlling features are set to their default setting in the
L3-bus and I2C-bus mode.
The reset time (see Fig.8) is determined by an external
capacitor which is connected between pin Vref and ground.
The reset time should be at least 1 µs for Vref < 1.25 V.
When VDDA(DAC) is switched off, the device will be reset
again for Vref < 0.75 V.
During the reset time the system clock should be running.
handbook, halfpage
3.0 V
VDDA(DAC)
25
Vref 28
C1 >
10 µF
8 k
RESET
CIRCUIT
8 k
UDA1342TS
MGU001
Fig.7 Power-on reset circuit.
2000 Mar 29
12

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