UPD98401AGD-MML Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD98401AGD-MML

ATM SAR CHIP

NEC => Renesas Technology 

µPD98401A

(2/2)

Pin Name

Pin No.

I/O

I/O Level

Function

TENBL_B

90

O

CMOS

Transmit Enable.

The TENBL_B signal indicates to a PHY device that data has been

output to Tx7 through Tx0 in the current clock cycle. This signal

remains high during reset and after reset.

FULL_B/

88

I

TTL

PHY Buffer Full/Tx Cell Available.

TxCLAV

The FULL_B signal notifies the µPD98401A that the input buffer of the

PHY device is full and that the device can receive no more data.

When the UTOPIA interface is in the octet-level handshake mode, the

PHY device inputs an inactive level to receive cell of data. In the cell-

level handshake mode, this signal indicates that the PHY device can

receive all the next one cell of data after the current cell has been

completely transferred

TCLK

92

O

CMOS

Transmit Clock.

This is a synchronization clock used to transfer cell data with the PHY

device at the transmission side. The system clock input to the CLK

pin is output from this pin as is.

(2) PHY device control interface

Pin Name

Pin No.

I/O

I/O Level

Function

PHRW_B

109

O

CMOS

PHY Read/Write.

The µPD98401A indicates the direction in which the PHY device is

controlled, by using PHRW_B. This signal goes low after reset.

1: Read

0: Write

PHOE_B

108

O

CMOS

PHY Output Enable.

The µPD98401A enables output from the PHY device by making

PHOE_B low

PHCE_B

103

O

CMOS

PHY Chip Enable.

The µPD98401A makes PHCE_B low to access a PHY device. This

signal goes high after reset.

PHINT_B

107

I

TTL

PHY Interrupt.

This is an interrupt input signal from a PHY device. The PHY device

indicates to the µPD98401A that it has an interrupt source, by

inputting a low level to PHINT_B. This signal goes high after reset.

8

Data Sheet S12100EJ3V0DS00

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