UPD98401AGD-MML Просмотр технического описания (PDF) - NEC => Renesas Technology

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Компоненты Описание

производитель

UPD98401AGD-MML

ATM SAR CHIP

NEC => Renesas Technology 

µPD98401A

PIN NAMES

ABRT_B

: Abort

AD31_AD0

: Address/Data

ASEL_B

: Slave Address Select

ATTN_B

: Attention/Burst Frame

CA17-CA0

: Control Memory Address

CBE_B3_CBE_B0 : Local Port Byte Enable

CD31-CD0

: Control Memory Data

CLK

: Clock

COE_B

: Control Memory Output Enable

CPAR3-CPAR0 : Control Memory Parity

CWE_B

: Control Memory Write Enable

DBMD

: DMA Bus Monitor Data

DBMF

: DMA Bus Monitor First

DBML

: DMA Bus Monitor Last

DBVC

: DMA Bus Monitor VC

DBMR

: DMA Bus Monitor Remaining

DR/W_B

: DMA Read/Write

EMPTY_B/RxCLAV : PHY Output Buffer Empty

ERR_B

: Error

FULL_B/TxCLAV : PHY Buffer Ful

GND

: Ground

GNT_B

: Grant

INITD

: Initialization Disable

INTR_B

: Interrupt

JCK

: JTAG Test Pin

JDI

: JTAG Test Pin

JDO

: JTAG Test Pin

JMS

: JTAG Test Pin

JRST_B

: JTAG Test Pin

OE_B

: Output Enable

PAR3-PAR0

: Bus Parity

PHCE_B

PHINT_B

PHOE_B

PHRW_B

RCLK

RDY_B

RENBL_B

RSOC

RST_B

Rx7-Rx0

SLE_B

SIZE2-SIZE0

SR/W_B

TCLK

TENBL_B

TSOC

TRF_B

Tx7-Tx0

VDD

: PHY Chip Enable

: PHY Interrupt

: PHY Output Enable

: PHY Read/Write

: Receive Clock

: Target Ready

: Receive Enable

: Receive Start Cell

: Reset

: Receive Data Bus

: Slave Select

: Burst Size

: Slave Read/Write

: Transmit Clock

: Transmit Enable

: Transmit Start of Cell

: Delay Select

: Transmit Data Bus

: Power Supply

Data Sheet S12100EJ3V0DS00

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