UPD98401AGD-MML Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD98401AGD-MML

ATM SAR CHIP

NEC => Renesas Technology 

µPD98401A

Pin Name

SR/W_B

Pin No.

68

SEL_B

69

ASEL_B

70

CLK

32

RST_B

29

INTR_B

71

I/O

I/O Level

Function

(3/3)

I

TTL

Slave Read/Write.

The SR/W_B signal determines the direction in which the slave is

accessed.

1: Read access

2: Write access

I

TTL

Slave Select.

This signal goes low (active) when the µPD98401A is accessed as a

slave. The SEL_B signal must goes low as soon as or after the

ASEL_B signal has gone low. An inactive period of at least 2 system

clock cycles must be inserted between when the SEL_B signal has

become inactive and when it becomes active again.

I

TTL

Slave Address Select.

The ASEL_B signal is used to select the direct address register of the

µPD98401A.

When a low level is input to ASEL_B, the µPD98401A samples the AD

bus at the first rising edge of CLK.

I

TTL

Clock.

This pin inputs the system clock. Input a clock in a range of 8 to 33

MHz.

I

TTL

Reset.

The RST_B signal initializes the µPD98401A (on starting, etc.). After

reset, the µPD98401A can start normal operation. When a low level is

input to RST_B, the internal state machine and registers of the

µPD98401A are reset, and all 3-state signals go into a high-

impedance state. The reset input is asynchronous. When this signal

is input during operation, the operating status at that time is lost. Hold

RST_B low at least for the duration of one clock. After reset, do not

access the µPD98401A for at least 20 clock cycles.

O

Nch open- Interrupt.

drain output This is an open-drain signal and must be pulled up.

INTR_B informs the CPU that the interrupt bit (unmasked) of the GSR

register is set.

Data Sheet S12100EJ3V0DS00

11

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