PM7328-BI Просмотр технического описания (PDF) - PMC-Sierra

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PM7328-BI

ATM LAYER SOLUTION

PMC-Sierra 

STANDARD PRODUCT

DATASHEET

PMC-2010142

ISSUE 2

PM7328 S/UNI-ATLAS-1K800

ATM LAYER SOLUTION

28. Backward Total Lost CLP0 cell count.

29. Backward Lost Fwd Monitoring PM cell count.

30. Backward Lost Backward Reporting PM cell count.

31. Total Transmitted CLP0+1 cell count.

32. Total Transmitted CLP0 cell count.

Statistics for PM sessions are held in on-chip RAM that can be read at any

time through the 16-bit general-purpose microprocessor port.

Paced insertion of PM cells is provided.

PM block size generation and termination is per-session programmable

ranging from 128 – 32768 cells.

Each of the 512 PM sessions can be configured to be a source, sink or

non-intrusive monitoring point of PM cells.

• OAM-Fault Management is provided on a per-connection basis in the ingress

and egress directions. Simultaneous segment and end-to-end F4 and F5 AIS,

RDI and CC cell generation, termination and monitoring is supported. Alarm

bits and interrupt masks are provided on a per-connection basis. F4 to F5 AIS

alarm splitting is provided in the Ingress direction. Paced insertion of FM cells

is provided.

• OAM-Loopback extraction (to a Microprocessor Cell Interface) is per-

connection configurable in both the ingress and egress directions.Includes a

FIFO buffered microprocessor bus interface for cell insertion and extraction

(in both the ingress and egress directions), Ingress and Egress VC Table

access, control and status monitoring and configuration of the device.

• Supports DMA access for cell extraction.

• Uses common external Synchronous Flow-Through SRAM (with or without

parity) for maintaining per-connection information. Separate SRAM’s are used

for the Ingress and Egress context tables.

• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board

test purposes.

• Provides a generic 16 bit microprocessor bus interface for configuration,

control and status monitoring.

• Low power 0.35 micron, 3.3 V CMOS technology with a 3.3 V UTOPIA (SCI-

PHY), 3.3/5 V Microprocessor I/O interfaces and 3.3 V external synchronous

SRAM interfaces.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC

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