AD6640AST(Rev0) Просмотр технического описания (PDF) - Analog Devices
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AD6640AST Datasheet PDF : 24 Pages
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AD6640–SPECIFICATIONS
DC SPECIFICATIONS (AVCC = +5 V, DVCC = +3.3 V; TMIN = –40؇C, TMAX = +85؇C)
Parameter
Test
AD6640AST
Temp
Level
Min
Typ
Max
Units
RESOLUTION
12
Bits
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)1
Integral Nonlinearity (INL)1
+25°C
I
Full
VI
Full
VI
+25°C
I
Full
V
GUARANTEED
–10
3.5
+10
–10
4.0
+10
–1.0
± 0.5
+1.5
± 1.25
mV
% FS
LSB
LSB
TEMPERATURE DRIFT
Offset Error
Gain Error
POWER SUPPLY REJECTION (PSRR)
REFERENCE OUT (VREF)2
ANALOG INPUTS (AIN, AIN)3
Analog Input Common-Mode Range4
Differential Input Voltage Range
Differential Input Resistance
Differential Input Capacitance
Full
V
Full
V
Full
V
Full
V
Full
V
Full
V
Full
IV
0.7
+25°C
V
50
100
± 0.5
2.4
VREF ± 0.05
2.0
0.9
1.1
1.5
ppm/°C
ppm/°C
mV/V
V
V
V p-p
kΩ
pF
POWER SUPPLY
Supply Voltage
AVCC
DVCC
Supply Current
IAVCC (AVCC = 5.0 V)
IDVCC (DVCC = 3.3 V)
POWER CONSUMPTION
Full
VI
4.75
5.0
5.25
V
Full
VI
3.0
3.3
5.25
V
Full
VI
Full
VI
Full
VI
135
160
mA
10
20
mA
710
865
mW
NOTES
1ENCODE = 20 MSPS
2If VREF is used to provide a dc offset to other circuits, it should first be buffered.
3The AD6640 is designed to be driven differentially. Both AIN and AIN should be driven at levels VREF ± 0.5 volts. The input signals should be 180 degrees out of phase to
produce a 2 V p-p differential input signal. See Driving the Analog Inputs section for more details.
4Analog input common-mode range specifies the offset range the analog inputs can tolerate in dc-coupled applications (see Figure 35 for more detail).
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS (AVCC = +5 V, DVCC = +3.3 V; TMIN = –40؇C, TMAX = +85؇C)
Parameter
Test
AD6640AST
Temp
Level
Min
Typ
Max
Units
LOGIC INPUTS (ENC, ENC)1
Encode Input Common-Mode Range2
Differential Input Voltage
Single-Ended Encode
Logic Compatibility3
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (VINH = 5 V)
Logic “0” Current (VINL = 0 V)
Input Capacitance
LOGIC OUTPUTS (D11–D0)4
Logic Compatibility
Logic “1” Voltage (DVCC = +3.3 V)
Logic “0” Voltage (DVCC = +3.3 V)
Logic “1” Voltage (DVCC = +5.0 V)
Logic “0” Voltage (DVCC = +5.0 V)
Output Coding
Full
IV
Full
IV
Full
VI
Full
VI
Full
VI
Full
VI
+25°C
V
Full
VI
Full
VI
Full
IV
Full
IV
0.2
0.4
2.0
0
500
–400
TTL/CMOS
650
–320
2.5
2.2
10
5.0
0.8
800
–200
CMOS
2.8
DVCC – 0.2
0.2
0.5
4.5
DVCC – 0.3
0.35
0.5
Twos Complement
V
V p-p
V p-p
V
V
µA
µA
pF
V
V
V
V
NOTES
1Best dynamic performance is obtained by driving ENC and ENC differentially. See Encoding the AD6640 section for more details. Performance versus ENC/ENC power is
shown in Figure 18 under Typical Performance Characteristics.
2For dc-coupled applications, Encode Input Common-Mode Range specifies the common-mode range the encode inputs can tolerate when driven differentially by minimum
differential input voltage of 0.4 V p-p. For differential input voltage swings greater than 0.4 V p-p, the common-mode range will change. The minimum value insures that the
input voltage on either encode pin does not go below 0 V. The maximum value insures that the input voltage on either encode pin does not go below 2.0 V or above AVCC (e.g.,
for a differential input swing of 0.8 V, the min and max common-mode specs become 0.4 V and 2.4 V respectively).
3ENC or ENC may be driven alone if desired, but performance will likely be degraded. Logic Compatibility specifications are provided to show that TTL or CMOS clock sources
will work. When driving only one encode input, bypass the complementary input to GND with 0.01 µF.
4Digital output load is one LCX gate.
Specifications subject to change without notice.
–2–
REV. 0
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