UT62L5128LC-70LI Просмотр технического описания (PDF) - Utron Technology Inc

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производитель

UT62L5128LC-70LI

512K X 8 BIT LOW POWER CMOS SRAM

Utron Technology Inc 



UTRON

Preliminary Rev. 0.7

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2,4)

Address

UT62L5128(I)

512K X 8 BIT LOW POWER CMOS SRAM

tRC

DOUT

tAA

tOH

tOH

Data Valid

READ CYCLE 2 ( CE and OE Controlled) (1,3,5,6)

t RC

Address

CE

t AA

t ACE

OE

t CLZ

t OE

Dout

HIGH-Z

t OLZ

t CHZ

t OHZ

t OH

Data Valid

Notes :

1. WE is HIGH for read cycle.

2. Device is continuously selected CE =VIL.

3. Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter.

4. OE is LOW.

5. tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

6. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ.

HIGH-Z

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

5

P80052

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