UT61L256LS-10 Просмотр технического описания (PDF) - Utron Technology Inc
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UT61L256LS-10 Datasheet PDF : 10 Pages
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Rev. 1.3
UTRON
UT61L256
32K X 8 BIT HIGH SPEED LOW VCC CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2,4)
tRC
Address
DOUT
tAA
tOH
tOH
Data Valid
READ CYCLE 2 ( CE and OE Controlled) (1,3,5,6)
Address
CE
OE
DOUT
tRC
tAA
tACE
tCLZ
High-z
tOE
tOLZ
tCHZ
tOHZ
tOH
Data valid
High-Z
Notes :
1. WE is HIGH for read cycle.
2. Device is continuously selected CE =VIL.
3. Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
6. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
P80023
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