HMP9701A Просмотр технического описания (PDF) - Intersil
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HMP9701A Datasheet PDF : 20 Pages
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HMP9701A
Testability
The HMP9701A provides a test mode to support the in cir-
cuit test capabilities provided by automatic test equipment
(ATE). In this mode, the HMP9701A drives its digital AC-Link
outputs (BIT_CLK and SDATA_IN) to a high impedance
state. This allows for in circuit testing of the digital controller
component of the sound subsystem.
The HMP9701A enters ATE test mode when SDATA_OUT is
sampled high by the trailing edge of RESET (see AC Timing
Diagrams). The HMP9701A will remain in test mode until a
“cold” reset returns the part to normal operation.
Control/Status Registers
The HMP9701A contains a bank of 16-bit control/status reg-
isters to control and monitor part operation. The control reg-
isters are accessed via the even addresses within the 6-bit
address space provided in Slot 1 of the Audio Output Frame.
The control/status register address map is given in Table 20.
Reset Register (Index 00h)
Writing any value to this register performs a register reset
that causes all registers to revert to their default values.
Reading this register returns the AC’97 ID code that
specifies the optional AC’97 features supported by the
HMP9701A. This register will read back 0001h to indicate
that the HMP9701A provides the optional ADC for a
dedicated MIC channel.
Master Volume Control Registers (Index 02h, 06h)
These registers manage the output audio volumes. Register
02h sets the master stereo volume (LINE_OUT_L,
LINE_OUT_R) and Register 06h controls the mono volume
(MONO_OUT). Each volume step corresponds to 1.5dB.
The MSB of both registers is the mute bit. When this bit is
set to 1 the level for that channel is set at -∞dB.
TABLE 11. MASTER VOLUME SETTINGS
MUTE
MX5...MX0
FUNCTION
0
00 0000
0dB Attenuation
0
01 1111
46.5dB Attenuation
0
1x xxxx
46.5dB Attenuation
1
xx xxxx
-∞dB Attenuation
Default Value: 8000h (0dB Gain with Mute On)
The HMP9701A supports 5 bits of gain control for the stereo
line out and mono out. The right and left stereo channels are
controlled via MR4:0 and ML4:0 respectively. The mono out-
put is controlled by MM4:0. Writing a “1” to MR5, ML5, or
MM5 will force the volume level to max attenuation, Mx4:0 =
11111 (46.5dB attenuation). Note: if these registers are writ-
ten with Mx5:0 = 1xxxx, they will read back Mx5:0 = 01111.
PC Beep Register (Index 0Ah)
This register controls the level of the PC Beep input. The PC
Beep is attenuated as specified by the contents of this regis-
ter and mixed equally into both the right and left output chan-
nels. The PC_BEEP input is attenuated in 3dB steps from
0dB to 45dB. The MSB of the register is the mute bit. When
this bit is set to 1 the level for that channel is set at - ∞dB.
TABLE 12. PC_BEEP ATTENUATION SETTINGS
MUTE
PV3:0
FUNCTION
0
0000
0dB Attenuation
0
1111
45dB Attenuation
1
xxxx
-∞dB Attenuation
Default Value: 8000h (0dB Gain w/ Mute on)
Input Volume Control (Index 0Ch- 18h)
These registers control the input gain/attenuate/mute (GAM)
blocks through which each of the analog mixer’s inputs pass.
Each GAM block has a 5-bit control that supports setting the
gain in increments of 1.5dB. A total gain range from +12dB to
-34.5dB is supported. The MSB of each register is a Mute bit
that will set the gain to -∞dB when programmed to 1. Note: reg-
ister 0Eh (Mic Volume Register) has an extra bit that is for a
20dB boost. When bit 6 is set to 1 the 20dB boost is on.
TABLE 13. ANALOG MIXER INPUT GAIN SETTINGS
MUTE
PV3:0
FUNCTION
0
00000
+12dB Gain
0
01000
0dB Gain
0
11111
-34.5dB Gain
1
xxxx
-∞dB Gain
Default: All GAM blocks set to Mute with 0dB Gain (see Table 20)
Record Select (Index 1Ah)
This register is used to select the record source for the left
and right record ADC’s. The selections are summarized
below in Table 14 and 15.
TABLE 14. RECORD SELECT RIGHT CHANNEL
SR2:0
RIGHT RECORD SOURCE
0
MIC
1
CD_R
2
VIDEO_R
3
AUX_R
4
LINE_IN_R
5
Stereo Mix Right
6
Mono Mix
7
PHONE
Default: 000 (MIC in)
8
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