HMP9701A Просмотр технического описания (PDF) - Intersil

Номер в каталоге

Компоненты Описание

производитель

HMP9701A

AC’97 Audio Codec

Intersil 

HMP9701A

TAG PHASE

20.8µs

(48kHz)

DATA PHASE

SYNC

BIT_CLK

12.288MHz

81.4ns

SDATA_OUT

VALID

FRAME

SLOT SLOT

1

2

SLOT

12

“0”

“0”

TIME SLOT “VALID” BITS

(“1” = TIME SLOT CONTAINS VALID DATA)

“1” = FRAME CONTAINS

VALID DATA

“0” BIT 19

BIT 0 BIT 19

BIT 0 BIT 19

BIT 0

SLOT 1

SLOT 2

SLOT 12

FIGURE 3. AC LINK AUDIO OUTPUT FRAME

The HMP9701A generates a serial bit clock (BIT_CLK) at

12.288MHz for synchronous data transfers on the AC Link.

Data is output on SDATA_IN by the rising edge of BIT_CLK,

and serial data is sampled on SDATA_OUT by the falling

edge of BIT_CLK. An audio frame transfer is initiated by the

assertion of SYNC for the 16 BIT_CLK’s comprising the Tag

Phase of the audio frame. The SYNC signal must be

asserted at a fixed 48kHz rate, and it can be derived by

dividing down the BIT_CLK.

The tag phase is a 16-bit data slot (Slot 0) wherein each bit

is a data valid flag for an associated time slot within the cur-

rent audio frame. A “1” in a given bit position of Slot 0 indi-

cates that the corresponding time slot within the audio frame

contains valid data. If the HMP9701A “tags” a slot invalid, it

will set the data bits comprising that slot to zero.

in the control and PCM output data slots is valid. The

remaining 8 bits in Slot 0 are ignored as they are associ-

ated with reserved data slots.

SYNC

HMP9701A SAMPLES HMP9701A SAMPLES

SYNC ASSERTION FIRST BIT OF AUDIO OUTPUT

BIT_CLK

SDATA_OUT

PREVIOUS

AUDIO FRAME

SLOT 1 SLOT 2

VALID

FRAME

AC Link Output Frame (SDATA_OUT)

The audio output frame contains data targeted for the

HMP9701A’s DAC inputs, and control registers. This data is

transmitted in slots 1 through 4 of the audio frame as shown

in Figure 2. The tag slot, Slot 0, is a special reserved time

slot containing 16 bits that tell the AC-link interface circuitry

the validity of the following data slots.

The HMP9701A is synchronized to the beginning of a new

audio output frame when SYNC makes a low to high transi-

tion and is sampled low by the falling edge of BIT_CLK as

shown in Figure 3. On the next rising of BIT_CLK, the

AC’97 controller drives SDATA_OUT with the first bit of slot

0 (Valid Frame bit) which is then sampled by the

HMP9701A on the subsequent falling edge of BCLK. The

controller drives the remaining audio frame bits out on

SDATA_OUT with each rising edge of BCLK, and the

HMP9701A samples these bits on the subsequent falling

edge.

The first bit of the output audio frame (Slot 0, bit 15) flags

the validity of the entire audio frame. If the “Valid Frame” bit

is a 1, this indicates that the current audio frame contains

at least one time slot of valid data. The HMP9701A moni-

tors the next 4-bit positions to determine whether the data

FIGURE 4. START OF AUDIO OUTPUT FRAME

The 20-bit data word in each time slot must be transmitted MSB

first. If the data word targeted for a time slot is less than 20 bits,

the data word must be MSB justified in the most significant bits

of the time slot with the unused bits set to zero. For example, an

8-bit audio sample would be transmitted in bits 19-12 of the

time slot with the trailing 12 bits set to zero. The MSB of the

audio sample would map to bit 19 of the time slot. Note: for the

playback of mono audio streams, the digital controller must

send the same sample to each PCM output channel.

Audio Output Slot 1: Control Address

The bits in Slot 1 are used to access the 16-bit control/status

registers within the HMP9701A. The address space allo-

cated in slot 1 allows up to 64 sixteen bit registers, however,

only the even registers are valid (see Control/Status register

section for a complete register map). The control registers

are read/writable to provide more robust testability. A read or

write command is initiated by setting the Read/Write bit (Bit

19) in Slot 1. A complete bit map for Slot 1 is given in the

Table 1. Note: control data will only be loaded into the target

registers if Slot 2 (Control Data) is flagged as being valid.

4

Share Link: