SMJ44400 Просмотр технического описания (PDF) - Austin Semiconductor
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SMJ44400 Datasheet PDF : 21 Pages
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Austin Semiconductor, Inc.
DRAM
SMJ44400
TIMING REQUIREMENTS (-55oC<TA<125oC or -40oC to +85oC; Vcc = 5V +10%)
SYM
PARAMETER
tRC Cycle time, random read or write1
-8
MIN MAX
150
-10
MIN MAX
180
-12
MIN MAX
210
UNIT
ns
tRWC Cycle time, read-write
205
245
285
ns
tPC Cycle time, page-mode read or write2
50
60
65
ns
tPRWC
tRASP
tRAS
tCAS
Cycle time, page-mode read-write
Pulse duration, page mode, RAS\ low3
Pulse duration, nonpage mode, RAS\ low3
Pulse duration, CAS\ low4
100
120
135
ns
80 100000 100 100000 120 100000 ns
80 10000 100 10000 120 10000 ns
20 10000 25 10000 30 10000 ns
tCP Pulse duration, CAS\ High
10
10
15
ns
tRP Pulse duration, RAS\ High (precharge)
60
70
80
ns
tWP Pulse duration, write
15
20
25
ns
tASC Setup time, column address before CAS\ low 0
0
0
ns
tASR Setup time, row address before RAS\ low
0
0
0
ns
tDS Setup time, data5
0
0
0
ns
tRCS Setup time, read before CAS\ low
0
0
0
ns
tCWL Setup time, W\ low before CAS\ high
20
25
30
ns
tRWL Setup time, W\ low before RAS\ high
20
25
30
ns
tWCS
Setup time, W\ low before CAS\ low
(early-write operation only)
0
0
0
ns
tWSR Setup time, W\ High (CBR refresh only)
10
10
10
ns
tCAH Hold time, column address after CAS\ low
15
20
20
ns
tDHR Hold time, data after RAS\ low
60
75
90
ns
tDH Hold time, data5
15
20
25
ns
tAR Hold time, column address after CAS\ low4
60
75
90
ns
tRAH Hold time, row address after RAS\ low
10
15
15
ns
tRCH Hold time, read after CAS\ High6
0
0
0
ns
tRRH Hold time, read after RAS\ High6
0
0
0
ns
tWCH
Hold time, write after CAS\ low
(early-write operation only)
15
20
25
ns
tWCR Hold time, write after RAS\ low4
60
75
90
ns
tWHR Hold time, W\ High (CBR refresh only)
10
10
10
ns
tOEH Hold time, OE\ command
20
25
30
ns
tROH Hold time, RAS\ referenced to OE\
20
25
30
ns
tAWD
Delay time, column address to W\ low
(read-write operation only)
70
80
90
ns
tCHR
Delay time, RAS\ low to CAS\ High
(CBR refresh only)
20
20
25
ns
tCRP Delay time, CAS\ High to RAS\ low
0
0
0
ns
tCSH Delay time, RAS\ low to CAS\ High
80
100
120
ns
tCSR
Delay time, CAS\ low to RAS\ low
(CBR refresh only)
10
10
10
ns
tCWD
Delay time, CAS\ low to W\ low
(read-write operation only)
50
60
70
ns
NOTES:
1. All cycle times assume tT = 5ns.
2. To assure tPC min, tASC should be > tCP.
3. In a read-write cycle, tRWD and tRWL must be observed.
4. In a read-write cycle, tCWD and tCWL must be observed.
5. Referenced to the later of CAS\ or W\ in write operations.
6. Either tRRH or tRCH must be satisfied for a read cycle.
SMJ44400
Rev. 2.0 10/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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