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SMJ44400

1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY

Austin Semiconductor 

Austin Semiconductor, Inc.

DRAM

SMJ44400

1M x 4 DRAM

DYNAMIC RANDOM-ACCESS

MEMORY

AVAILABLE AS MILITARY

SPECIFICATIONS

• SMD 5962-90847

• MIL-STD-883

FEATURES

• Organized 1,048,576 x 4

• Single +5V ±10% power supply

• Enhanced Page-Mode operation for faster memory access

P Higher data bandwidth than conventional page-mode

parts

P Random Single-Bit Access within a row with a column

address

• CAS\-Before-RAS\ (CBR) Refresh

• Long Refresh period: 1024-cycle Refresh in 16ms (Max)

• 3-State unlatched Output

• Low Power Dissipation

• All Inputs/Outputs and Clocks are TTL Compatible

• Processing to MIL-STD-883, Class B available

OPTIONS

• Timing

80ns access

100ns access

120ns access

MARKING

-80

-10

-12

• Package(s)

Ceramic DIP (400mils)

Ceramic Flatpack

JD No. 113

HR No. 308

• Operating Temperature Ranges

Military (-55oC to +125oC) M

GENERAL DESCRIPTION

The SMJ44400 is a series of 4,194,304-bit dynamic ran-

dom-access memories (DRAMs), organized as 1,048,576

words of four bits each. This series employs state-of-the-art

technology for high performance, reliability, and low-power

operation.

The SMJ44400 features maximum row access times of

80ns, 100ns, and 120ns. Maximum power dissipation is as

low as 360mW operating and 22mW standby.

All inputs and outputs, including clocks, are compatible

with Series 54 TTL. All addressses and data-in lines are latched

on-chip to simplify system design. Data out is unlatched to

allow greater system flexibility.

PIN ASSIGNMENT

(Top View)

20-Pin DIP (JD)

20-Pin Flatpack (HR)

(400 MIL)

DQ1 1

DQ2 2

W\ 3

RAS\ 4

A9 5

A0 6

A1 7

A2 8

A3 9

Vcc 10

20 Vss

19 DQ4

18 DQ3

17 CAS\

16 OE\

15 A8

14 A7

13 A6

12 A5

11 A4

Pin Name

Function

A0 - A9 Address Inputs

CAS\ Column-Address Strobe

DQ1 - DQ4 Data Inputs/Outputs

OE\ Output Enable

RAS\ Row-Address Strobe

W\ Write Enable

Vcc 5V Supply

Vss Ground

The SMJ44400 is offered in a 400-mil, 20-pin ceramic

side-brazed dual-in-line package (JD suffix) and a 20-pin

ceramic flatpack (HR suffix) that are characterized for

operation from -55°C to +125°C.

OPERATION

Enhanced Page Mode

Enhanced page-mode operation allows faster memory

access by keeping the same row address while selecting

random column addresses. The time for row-address setup

and hold and address multiplex is eliminated. The maximum

number of columns that can be accessed is determined by the

maximum RAS\ low time and the CAS\ page cycle time used.

With minimum CAS\ page cycle time, all 1024 columns

specified by column addresses A0 through A9 can be accessed

without intervening RAS\ cycles.

Unlike conventional page-mode DRAMs, the column-

address buffers in this device are activated on the

For more products and information

please visit our web site at

www.austinsemiconductor.com

SMJ44400

Rev. 2.0 10/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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