SMJ44400 Просмотр технического описания (PDF) - Austin Semiconductor

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SMJ44400

1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY

Austin Semiconductor 

Austin Semiconductor, Inc.

READ-WRITE CYCLE TIMING

DRAM

SMJ44400

(1)

NOTES:

1. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access tiems as the outputs are driven when

CAS\ and OE\ are low.

SMJ44400

Rev. 2.0 10/01

11

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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