WM8190 Просмотр технического описания (PDF) - Wolfson Microelectronics plc

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WM8190

(8 + 6) Bit Output 14-bit CIS/CCD AFE/Digitiser

Wolfson Microelectronics plc 

Advanced Information

WM8190

MCLK

VSMP

VS

RS/CL (CDSREF = 00)

RS/CL (CDSREF = 01)

RS/CL (CDSREF = 10)

RS/CL (CDSREF = 11)

Figure 9 Reset Sample and Clamp Timing

For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed

with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described

above. The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this

mode.

OFFSET ADJUST AND PROGRAMMABLE GAIN

The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset

DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset for each

channel are independently programmable by writing to control bits DAC[7:0] and PGA[7:0].

In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order

(Red → Green → Blue → Red…) by pulsing the ACYC/RLC pin, or controlled via the FME,

ACYCNRLC and INTM[1:0] bits. Refer to the Line-by-Line Operation section for more details.

ADC INPUT BLACK LEVEL ADJUST

The output from the PGA must be offset to match the full-scale range of the ADC. For negative-going

input signals, a black level (zero differential) output from the PGA should be offset to the top of the

ADC range. For positive going input signal the black level should be offset to the bottom of the ADC

range. This is achieved by writing to control bits PGAFS[1:0].

OVERALL SIGNAL FLOW SUMMARY

Figure 10 represents the processing of the video signal through the WM8190.

INPUT

SAMPLING OFFSET DAC PGA

BLOCK

BLOCK BLOCK

V1

V2

V3

V IN

+-

++

X

analog

CDS = 1

VRESET

CDS = 0

PGA gain

A = 208/(283-PGA[7:0])

ADC BLOCK

x (16383/V FS)

+0 if PGAFS[1:0]=11

+16383 if PGAFS[1:0]=10

+8191 if PGAFS[1:0]=0x

OUTPUT

INVERT

BLOCK

D1

digital

TO MULTI-

PLEXER FOR

8-BIT OUTPUT

D2

OP[13:0]

D2 = D1 if INVOP = 0

D2 = 16383-D1 if INVOP = 1

VVRLC

RLCEXT=1 RLCEXT=0

Offset 260mV*(DAC[7:0]-127.5)/127.5

DAC

VIN is RINP or GINP or BINP

VRESET is VIN sampled during reset clamp

VVRLC is voltage applied to VRLC pin

RLC

DAC V RLCSTEP*RLCV[3:0] + VRLCBOT

CDS, RLCEXT,RLCV[3:0], DAC[7:0],

PGA[7:0], PGAFS[1:0] and INVOP are set

by programming internal control registers.

CDS=1 for CDS, 0 for non-CDS

Figure 10 Overall Signal Flow

WOLFSON MICROELECTRONICS LTD

AI Rev 3.0 August 1999

11

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