WM8190 Просмотр технического описания (PDF) - Wolfson Microelectronics plc
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WM8190 Datasheet PDF : 25 Pages
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WM8190
C IN
RINP
EXTERNAL VRLC
VRLC/
VBIAS
Advanced Information
RLC/ACYC MCLK VSMP
TIMING CONTROL
CL
RS
VS
FROM CONTROL
INTERFACE
2
1
RLC
S/H
S/H
CDS
CDS
4-BIT
RLC DAC
VRLCEXT
+
+
TO OFFSET DAC
-
INPUT SAMPLING
BLOCK FOR RED
CHANNEL
FROM CONTROL
INTERFACE
Figure 7 Reset Level Clamping and CDS Circuitry
If auto-cycling is not required, RLC can be selected by pin RLC/ACYC. Figure 8 illustrates control of
RLC for a typical CCD waveform, with CL applied during the reset period.
The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during
each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal
CL pulse on the next reset level. The position of CL can be adjusted by using control bits
CDSREF[1:0] (Figure 9).
If auto-cycling is required, pin RLC/ACYC is no longer available for this function and control bit
RLCINT determines whether clamping is applied.
MCLK
VSMP
RLC/ACYC
1
X
X
Programmable Delay
CL
(CDSREF = 01)
0
X
X
0
INPUT VIDEO
RGB
RGB
RLC on this Pixel
RGB
No RLC on this Pixel
Figure 8 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL
The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits
RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit
RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit
VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.
CDS/NON-CDS PROCESSING
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel
common mode noise. For CDS operation, the video level is processed with respect to the video reset
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must
be set to 1 (default), this controls switch 2 (Figure 7) and causes the signal reference to come from
the video reset level. The time at which the reset level is sampled, by clock Rs/CL, is adjustable by
programming control bits CDSREF[1:0], as shown in Figure 9.
WOLFSON MICROELECTRONICS LTD
AI Rev 3.0 August 1999
10
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