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SI5324C-C-GM

ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Silicon Laboratories 

Si5324

Table 3. AC Characteristics

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Single-Ended Reference Clock Input Pin XA (XB with cap to GND)

Input Resistance

XARIN RATE[1:0] = LM, ML, MH,

—

12

—

k

or HM, ac coupled

Input Voltage Swing

XAVPP RATE[1:0] = LM, ML, MH,

0.5

—

1.2

VPP

or HM, ac coupled

Differential Reference Clock Input Pins (XA/XB)

Input Voltage Swing

XA/XBVPP RATE[1:0] = LM, ML, MH,

0.5

—

2.4

VPP

or HM

CKINn Input Pins

Input Frequency

CKNF

0.002

—

Input Duty Cycle

CKNDC

Whichever is smaller

40

—

(Minimum Pulse Width)

(i.e., the 40% / 60%

limitation applies only

to high frequency

clocks)

2

—

710

MHz

60

%

—

ns

Input Capacitance

CKNCIN

Input Rise/Fall Time

CKNTRF

20–80%

See Figure 2

CKOUTn Output Pins

(See ordering section for speed grade vs frequency limits)

Output Frequency

(Output not configured

for CMOS or

Disabled)

CKOF

N1  6

N1 = 5

N1 = 4

—

—

3

pF

—

—

11

ns

0.002

—

970

—

1.213

—

945

1134

1.4

MHz

MHz

GHz

Maximum Output

Frequency in CMOS

Format

CKOF

—

—

212.5

MHz

Notes:

1. Input to output phase skew after an ICAL is not controlled and can assume any value.

2. Lock and settle time performance is dependent on the frequency plan, the XAXB reference frequency, and LOCKT

setting (see application note, “AN803: Lock and Settling Time Considerations for Si5324/27/69/74 Any-Frequency

Jitter Attenuating Clock ICs”. Visit the Silicon Labs Technical Support web page at:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding

the lock time of your frequency plan.

3. LOCKT = 3.3 ms

Rev. 1.1

9

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