SI5319 Просмотр технического описания (PDF) - Silicon Laboratories
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SI5319 Datasheet PDF : 16 Pages
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Si5319
Pin # Pin Name I/O Signal Level
Description
23 SDA_SDO I/O
LVCMOS
Serial Data.
In I2C control mode (CMODE = 0), this pin functions as the bidirec-
tional serial data port.
In SPI control mode (CMODE = 1), this pin functions as the serial data
output.
25
A1
I
LVCMOS Serial Port Address.
24
A0
In I2C control mode (CMODE = 0), these pins function as hardware
controlled address bits. The I2C address is 1101 [A2] [A1] [A0].
In SPI control mode (CMODE = 1), these pins are ignored.
These pins have a weak pull-down.
26
A2_SS
I
LVCMOS Serial Port Address/Slave Select.
In I2C control mode (CMODE = 0), this pin functions as a hardware
controlled address bit [A2].
In SPI control mode (CMODE = 1), this pin functions as the slave
select input.
This pin has a weak pull-down.
27
SDI
I
LVCMOS Serial Data In.
In I2C control mode (CMODE = 0), this pin is ignored.
In SPI control mode (CMODE = 1), this pin functions as the serial data
input.
This pin has a weak pull-down.
29 CKOUT– O
28 CKOUT+
Multi
Output Clock.
Differential output clock with a frequency range of 10 MHz to
1.4175 GHz. Output signal format is selected by SFOUT1_REG regis-
ter bits. Output is differential for LVPECL, LVDS, and CML compatible
modes. For CMOS format, both output pins drive identical single-
ended clock outputs.
36 CMODE I
LVCMOS
Control Mode.
Selects I2C or SPI control mode for the Si5319.
0 = I2C Control Mode
1 = SPI Control Mode
GND
PAD
GND
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).
Preliminary Rev. 0.3
9
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