SI5319 Просмотр технического описания (PDF) - Silicon Laboratories

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SI5319

ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Silicon Laboratories 

Si5319

4. Package Outline: 36-Pin QFN

Figure 4 illustrates the package details for the Si5319. Table 3 lists the values for the dimensions shown in the

illustration.

Figure 4. 36-Pin Quad Flat No-lead (QFN)

Table 3. Package Dimensions

Symbol

Millimeters

Symbol

Millimeters

Min

Nom

Max

Min

Nom

Max

A

0.80

0.85

0.90

L

0.50

0.60

0.70

A1

0.00

0.02

0.05

θ

—

—

12º

b

0.18

0.25

0.30

aaa

—

—

0.10

D

6.00 BSC

bbb

—

—

0.10

D2

3.95

4.10

4.25

ccc

—

—

0.08

e

0.50 BSC

ddd

—

—

0.10

E

6.00 BSC

eee

—

—

0.05

E2

3.95

4.10

4.25

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC outline MO-220, variation VJJD.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body

Components.

Preliminary Rev. 0.3

11

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