SI5317 Просмотр технического описания (PDF) - Silicon Laboratories

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SI5317

PIN-CONTROLLED 1–710 MHZ JITTER CLEANING CLOCK

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Si5317

Table 2. DC Characteristics (Continued)

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Weak Internal Input

Pull-down Resistor

3-Level Input Pins

Symbol

RPDN

Test Condition

Min Typ Max Units

—

75

—

k

Input Voltage Low

Input Voltage Mid

Input Voltage High

Input Low Current

Input Mid Current

Input High Current

LVCMOS Output Pins

VILL

VIMM

VIHH

IILL2

IIMM2

IIHH2

—

— 0.15 x VDD V

0.45 x VDD — 0.55 x VDD V

0.85 x VDD —

—

V

–20

—

—

µA

–2

—

2

µA

—

—

20

µA

Output Voltage Low

VOL

IO = 2 mA

—

—

0.4

V

VDD = 1.62 V

IO = 2 mA

VDD = 2.97 V

—

—

0.4

V

Output Voltage High

VOH

IO = –2 mA

VDD = 1.62 V

VDD – 0.4 —

—

V

IO = –2 mA

VDD = 2.97 V

VDD – 0.4 —

—

V

Single-Ended Reference Clock Input Pin XA (XB with cap to gnd)

Input Resistance

XARIN

XTAL/RefCLK

8.5

10

11.5

k

Input Voltage Level Limits

XAVIN

RATE[1:0] = LM, ML, MH, or

HM

0

—

1.2

V

Input Voltage Swing

XAVPP

0.5

—

1.2

VPP

Differential Reference Clock Input Pins (XA/XB)

Input Resistance

XA/XBRIN

XTAL/RefCLK

8.5

10

11.5

k

Differential Input Voltage

Level Limits

XA/XBVIN

RATE[1:0] = LM, ML, MH, or

HM

0

—

1.2

V

Input Voltage Swing

XAVPP/XBVPP

0.5

—

1.2 VPP, each

Notes:

1. LVPECL outputs require VDD > 2.25 V.

2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most

designs, an external resistor voltage divider is recommended.

3. No overshoot or undershoot.

Preliminary Rev. 0.15

7

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