SI5317 Просмотр технического описания (PDF) - Silicon Laboratories

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SI5317

PIN-CONTROLLED 1–710 MHZ JITTER CLEANING CLOCK

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Si5317

Table 2. DC Characteristics (Continued)

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Symbol

Test Condition

Min Typ Max Units

Output Short to VDD

CKOISC+

VDD = 3.63 V

CML, LVDS, LVPECL

—

25

30

mA

VDD = 1.89 V

CML, LVDS

—

25

30

mA

VDD = 3.63 V

CMOS

—

190 200

mA

VDD = 1.89 V

CMOS

—

70

80

mA

Differential Output

Resistance

Common Mode Output

Resistance (to VDD)

CKORD

CKORCM

Disable

CML, LVPECL, LVDS,

Disable

CML, LVPECL, LVDS

Disable

—

1.5

2

µA

170 200 230



85

100 115



1

—

—

M

Output Voltage Low

Output Voltage High

CKOVOLLH

CKOVOHLH

CMOS

VDD = 1.71 V

CMOS

—

—

0.4

V

0.8 x VDD —

—

V

Output Drive Current

CKOIO

CMOS

Driving into CKOVOL for out-

put low or CKOVOH for output

high. CKOUT+ and CKOUT–

shorted externally.

2-Level LVCMOS Input Pins

VDD = 1.71 V

VDD = 2.97 V

7.5

—

—

mA

32

—

—

mA

Input Voltage Low

VIL

VDD = 1.71 V

—

—

0.5

V

VDD = 2.25 V

—

—

0.7

V

VDD = 2.97 V

—

—

0.8

V

Input Voltage High

VIH

VDD = 1.89 V

1.4

—

—

V

VDD = 2.25 V

1.8

—

—

V

VDD = 3.63 V

2.5

—

—

V

Input Low Current

IIL

—

—

50

µA

Input High Current

IIH

—

—

50

µA

Weak Internal Input Pull-up

Resistor

RPUP

—

75

—

k

Notes:

1. LVPECL outputs require VDD > 2.25 V.

2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most

designs, an external resistor voltage divider is recommended.

3. No overshoot or undershoot.

6

Preliminary Rev. 0.15

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