SI5317 Просмотр технического описания (PDF) - Silicon Laboratories

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SI5317

PIN-CONTROLLED 1–710 MHZ JITTER CLEANING CLOCK

Silicon Laboratories 

Si5317

1. Electrical Specifications

Table 1. Recommended Operating Conditions

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Temperature Range

Supply Voltage

Symbol

TA

VDD

Test Condition

3.3 V nominal

2.5 V nominal

1.8 V nominal

Min

Typ

Max Unit

–40

25

85

ºC

2.97

3.3

3.63

V

2.25

2.5

2.75

V

1.71

1.8

1.89

V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

Table 2. DC Characteristics

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Supply Current (Supply

current is independent of

VDD)

CKIN Input Pin

Symbol

IDD

Test Condition

LVPECL Format

622.08 MHz Out

All CKOUTs Enabled1

LVPECL Format

622.08 MHz Out

Only 1 CKOUT Enabled1

CMOS Format

19.44 MHz Out

All CKOUTs Enabled2

CMOS Format

19.44 MHz Out

Only CKOUT1 Enabled2

Min Typ Max Units

—

251 279

mA

—

217 243

mA

—

204 234

mA

—

194 220

mA

Input Common Mode

Voltage

(Input Threshold Voltage)

VICM

Input Resistance

Input Voltage Level Limits

Single-ended Input Voltage

Swing

CKNRIN

CKNVIN

VISE

1.8 V ± 5%

2.5 V ± 10%

3.3 V ± 10%

Single-ended

See note 3

fCKIN < 212.5 MHz

See Figure 2.

0.9

—

1.4

V

1.0

—

1.7

V

1.1

—

1.95

V

20

40

60

k

0

—

VDD

V

0.2

—

—

VPP

fCKIN > 212.5 MHz

See Figure 2.

0.25

—

—

VPP

Notes:

1. LVPECL outputs require VDD > 2.25 V.

2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most

designs, an external resistor voltage divider is recommended.

3. No overshoot or undershoot.

4

Preliminary Rev. 0.15

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