SI5316 Просмотр технического описания (PDF) - Silicon Laboratories

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SI5316

PRECISION CLOCK JITTER ATTENUATOR

Silicon Laboratories 

Si5316

Table 1. Performance Specifications (Continued)

(VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

External Reference Jitter

JPKEXTN

—

Transfer

Phase Noise

CKOPN

fOUT = 622.08 MHz

—

100 Hz offset

1 kHz offset

—

10 kHz offset

—

100 kHz offset

—

1 MHz offset

—

Subharmonic Noise

SPSUBH Phase Noise @ 100 kHz

—

Offset

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

dB

TBD dBc/Hz

TBD

TBD

TBD

TBD

TBD

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc

Spurious Noise

SPSPUR

Max spur @ n x F3

—

(n > 1, n x F3 < 100 MHz)

TBD

TBD

dBc

Package

Thermal Resistance

θJA

Junction to Ambient

Still Air

—

38

—

ºC/W

Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision

Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.

Table 2. Absolute Maximum Ratings

Parameter

Symbol

Value

Unit

DC Supply Voltage

LVCMOS Input Voltage

Operating Junction Temperature

Storage Temperature Range

ESD HBM Tolerance (100 pF, 1.5 kΩ)

VDD

–0.5 to 3.6

V

VDIG

–0.3 to (VDD + 0.3)

V

TJCT

–55 to 150

ºC

TSTG

–55 to 150

ºC

2

kV

ESD MM Tolerance

200

V

Latch-Up Tolerance

JESD78 Compliant

Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods of time may affect device reliability.

Preliminary Rev. 0.24

3

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