SI5315 Просмотр технического описания (PDF) - Silicon Laboratories

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SI5315

SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER

Silicon Laboratories 

Si5315

Table 3. AC Characteristics (Continued)

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Symbol

Test Condition

Min Typ Max Units

LVCMOS Output Pins

Rise/Fall Times

tRF

CLOAD = 20 pf

—

25

—

ns

See Figure 2

LOSn Trigger Window

LOSTRIG

From last CKINn  to

internal detection of LOSn

—

—

750 µs

Time to Clear LOL after LOS

Cleared

tCLRLOL

LOS to  LOL

Assume Fold=Fnew,

Stable XA-XB reference

—

10

—

ms

PLL Performance

Output Clock Skew

Phase Change Due to

Temperature Variation

tSKEW

of CKOUTn to CKOUTn

—

—

100 ps

tTEMP Maximum phase change from

—

300

500

ps

–40 to +85 °C

Lock Time

tLOCKHW RST with valid CKIN to LOL; —

1200

—

ms

BW = 100 Hz

Closed Loop Jitter Peaking

Jitter Tolerance

JPK

JTOL

— 0.05 0.1 dB

See 4.2.3. "Jitter Toler- ns pk-

ance" on page 18.

pk

Minimum Reset Pulse Width

tRSTMIN

1

—

—

µs

Output Clock Initial Phase Step

tP_STEP

During clock switch CKIN > 19.44

MHz

—

100

200

ps

Holdover Frequency Historical

Averaging Time

tHISTAVG

—

6.7

—

sec

Holdover Frequency Historical

Delay Time

tHISTDEL

— 26.2

—

ms

Spurious Noise

SPSPUR

Max spur @ n x f3

(n > 1, n x f3 < 100 MHz)

—

–75

— dBc

Notes:

1. Assumes N3 does not equal 1. IF N3 = 1, CKNDC = 50 µs.

2. Refers to Si5315A speed grade.

3. Refers to Si5315B speed grade.

Rev. 1.0

9

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