SI5315 Просмотр технического описания (PDF) - Silicon Laboratories

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SI5315

SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER

Silicon Laboratories 

Si5315

Table 3. AC Characteristics

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Symbol

Test Condition

Min Typ Max Units

Input Frequency

CKINn Input Pins

CKNF

0.008 — 644.53 MHz

Input Duty Cycle (Minimum

Pulse Width)

CKNDC

Whichever is smaller1

40

—

60

%

2

—

—

ns

Input Capacitance

Input Rise/Fall Time

CKNCIN

CKNTRF

20–80%

See Figure 2

—

—

3

pF

—

—

11

ns

CKOUTn Output Pins

Output Frequency (Output not

configured for CMOS or disable) CKOF

Note 2

Note 3

0.008 — 644.53 MHz

0.008 —

125 MHz

Maximum Output Frequency in CKOFMC

CMOS Format

—

— 161.13 MHz

Output Rise/Fall (20–80%) at CKOTRF Output not configured for CMOS —

230

350

ps

644.5313 MHz

or disabled, see Figure 2

Single Ended Output Rise/Fall

(20–80%)

CKOTRF

CMOS Output

VDD = 1.62

Cload = 5 pF

CMOS Output

VDD = 2.97

Cload = 5 pF

—

—

8

ns

—

—

2

ns

Output Duty Cycle Differential

Uncertainty

CKODC

100  Load

Line to Line

Measured at 50% Point

(not for CMOS)

—

—

±40 ps

LVCMOS Pins

Input Capacitance

Cin

Notes:

1. Assumes N3 does not equal 1. IF N3 = 1, CKNDC = 50 µs.

2. Refers to Si5315A speed grade.

3. Refers to Si5315B speed grade.

—

—

3

pF

8

Rev. 1.0

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