SI5315 Просмотр технического описания (PDF) - Silicon Laboratories

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SI5315

SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER

Silicon Laboratories 

Si5315

Table 2. DC Characteristics (Continued)

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Symbol

Test Condition

Min Typ Max Units

LVCMOS Output Pins

Output Voltage Low

VOL

IO = 2 mA

—

—

0.4

V

VDD = 1.62 V

IO = 2 mA

VDD = 2.97 V

—

—

0.4

V

Output Voltage High

VOH

IO = –2 mA

VDD – 0.4 —

—

V

VDD = 1.62 V

IO = –2 mA

VDD – 0.4 —

—

V

VDD = 2.97 V

Disabled Leakage Current

IOZ

RST = 0

–100 —

100

µA

Single-Ended Reference Clock Input Pin XA (XB with Cap to Gnd)

Input Resistance

XARIN

XTAL/CLOCK = M

Input Voltage Level Limits

XAVIN

Input Voltage Swing

XAVPP

Differential Reference Clock Input Pins (XA/XB)

—

12

—

k

0

—

1.2

V

0.5

—

1.2

VPP

Input Resistance

Differential Input Voltage

Level Limits

XA/XBRIN

XA/XBVIN

XTAL/CLOCK = M

—

12

—

k

0

—

1.2

V

Input Voltage Swing

XAVPP/XBVPP

0.5

—

2.4

VPP

Notes:

1. Refers to Si5315A speed grade.

2. Refers to Si5315B speed grade.

3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11.

Rev. 1.0

7

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