SI5315 Просмотр технического описания (PDF) - Silicon Laboratories

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SI5315

SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER

Silicon Laboratories 

Si5315

Table 2. DC Characteristics (Continued)

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Symbol

Test Condition

Min Typ Max Units

Output Drive Current

CKOIO

CMOS

Driving into CKOVOL for out-

put low or CKOVOH for out-

put high. CKOUT+ and

CKOUT– shorted externally.

2-Level LVCMOS Input Pins

VDD = 1.71 V

VDD = 2.97 V

7.5

—

—

mA

32

—

—

mA

Input Voltage Low

VIL

Input Voltage High

VIH

Input Low Current

Input High Current

Weak Internal Input Pull-up

Resistor

IIL

IIH

RPUP

VDD = 1.71 V

VDD = 2.25 V

VDD = 2.97 V

VDD = 1.89 V

VDD = 2.25 V

VDD = 3.63 V

—

—

0.5

V

—

—

0.7

V

—

—

0.8

V

1.4

—

—

V

1.8

—

—

V

2.5

—

—

V

—

—

50

µA

—

—

50

µA

—

75

—

k

Weak Internal Input

Pull-down Resistor

RPDN

—

75

—

k

3-Level Input Pins

Input Voltage Low

VILL

—

— 0.15 x VDD V

Input Voltage Mid

VIMM

0.45 x VDD — 0.55 x VDD V

Input Voltage High

VIHH

0.85 x VDD —

—

V

Input Low Current

IILL

See note 3.

–20

—

—

µA

Input Mid Current

IIMM

See note 3.

–2

—

2

µA

Input High Current

IIHH

See note 3.

—

—

20

µA

Notes:

1. Refers to Si5315A speed grade.

2. Refers to Si5315B speed grade.

3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11.

6

Rev. 1.0

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